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f0df0d6a14
Refreshed all patches. Compile-tested on: ipq40xx, apm821xx Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
60 lines
1.8 KiB
Diff
60 lines
1.8 KiB
Diff
From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Wed, 7 Sep 2016 16:44:28 +0530
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Subject: PCI: qcom: Force GEN1 support
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Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -122,6 +122,8 @@
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#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define SLV_ADDR_SPACE_SZ 0x10000000
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+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
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+
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#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
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struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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@@ -212,6 +214,7 @@ struct qcom_pcie {
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struct phy *phy;
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struct gpio_desc *reset;
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const struct qcom_pcie_ops *ops;
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+ uint32_t force_gen1;
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};
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#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
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@@ -504,6 +507,11 @@ static int qcom_pcie_init_2_1_0(struct q
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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+ if (pcie->force_gen1) {
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+ writel_relaxed((readl_relaxed(
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+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
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+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
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+ }
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/* Set the Max TLP size to 2K, instead of using default of 4K */
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@@ -1367,6 +1375,8 @@ static int qcom_pcie_probe(struct platfo
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struct dw_pcie *pci;
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struct qcom_pcie *pcie;
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int ret;
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+ uint32_t force_gen1 = 0;
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+ struct device_node *np = pdev->dev.of_node;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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@@ -1397,6 +1407,9 @@ static int qcom_pcie_probe(struct platfo
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goto err_pm_runtime_put;
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}
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+ of_property_read_u32(np, "force_gen1", &force_gen1);
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+ pcie->force_gen1 = force_gen1;
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+
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
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pcie->parf = devm_ioremap_resource(dev, res);
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if (IS_ERR(pcie->parf)) {
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