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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
227 lines
8.1 KiB
Diff
227 lines
8.1 KiB
Diff
From 883745d4728e524babfe7d04cbb8a925c22aa6b5 Mon Sep 17 00:00:00 2001
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From: Changhuang Liang <changhuang.liang@starfivetech.com>
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Date: Mon, 13 Nov 2023 14:46:50 +0800
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Subject: [PATCH 097/116] media: starfive: Update ISP initialzation
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ISP compatible stf_isp_ctrl and libcamera.
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Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
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---
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.../platform/starfive/v4l2_driver/stf_isp.c | 55 ++++++++-----------
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1 file changed, 24 insertions(+), 31 deletions(-)
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--- a/drivers/media/platform/starfive/v4l2_driver/stf_isp.c
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+++ b/drivers/media/platform/starfive/v4l2_driver/stf_isp.c
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@@ -402,7 +402,7 @@ static int isp_set_ctrl_cfa(struct stf_i
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reg_write(ispbase, reg_addr, ((u32)(cfg->cross_cov & 0x3) << 4) | (cfg->hv_width & 0xf));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -419,7 +419,7 @@ static int isp_set_ctrl_ctc(struct stf_i
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reg_value |= ((u32)(cfg->max_gt & 0x3ff) << 16) | (cfg->min_gt & 0x3ff);
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reg_write(ispbase, reg_addr, reg_value);
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -434,7 +434,7 @@ static int isp_set_ctrl_dbc(struct stf_i
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reg_write(ispbase, reg_addr, ((u32)(cfg->bad_gt & 0x3ff) << 16) | (cfg->bad_xt & 0x3ff));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -459,7 +459,7 @@ static int isp_set_ctrl_dnyuv(struct stf
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reg_write(ispbase, reg_addr + 36, CREATE_REG_VALUE(u16, &cfg->uv_curve[4], 2, 0x3ff, 16));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -472,7 +472,7 @@ static int isp_set_ctrl_gmargb(struct st
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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for(i = 0; i < 15; i++, curve++, reg_addr += 4)
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reg_write(ispbase, reg_addr, ((u32)curve->sg_val << 16) | (curve->g_val & 0x3ff));
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@@ -490,7 +490,7 @@ static int isp_set_ctrl_lccf(struct stf_
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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reg_write(ispbase, reg_addr, ((u32)(setting->circle.center_y & 0x7fff) << 16) | (setting->circle.center_x & 0x7fff));
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reg_write(ispbase, reg_addr + 8, setting->circle.radius & 0xf);
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reg_addr += 0x90;
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@@ -498,7 +498,7 @@ static int isp_set_ctrl_lccf(struct stf_
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reg_write(ispbase, reg_addr, CREATE_REG_VALUE(u16, params, 2, 0x1fff, 16));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -511,7 +511,7 @@ static int isp_set_ctrl_obc(struct stf_i
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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reg_write(ispbase, reg_addr, ((u32)(setting->win_size.height & 0xf) << 4) | (setting->win_size.width & 0xf));
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reg_addr += 0x2ac; //0x2e0
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@@ -519,7 +519,7 @@ static int isp_set_ctrl_obc(struct stf_i
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reg_write(ispbase, reg_addr, CREATE_REG_VALUE(u8, params, 4, 0xff, 8));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -535,7 +535,7 @@ static int isp_set_ctrl_oecf(struct stf_
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void __iomem *ispbase = vin->isp_base;
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u32 x, y, slope;
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s32 i;
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-
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+
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for(i = 0; i < 32; i++, reg_x_addr += 4, reg_y_addr += 4, reg_s_addr += 4) {
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x = pts->x & 0x3ff;
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y = pts->y & 0x3ff;
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@@ -565,12 +565,12 @@ static int isp_set_ctrl_r2y(struct stf_i
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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for(i = 0; i < 9; i++, reg_addr += 4)
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reg_write(ispbase, reg_addr, (u32)(params[i] & 0x1ff));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -584,7 +584,7 @@ static int isp_set_ctrl_sat(struct stf_i
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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for(i = 0; i < 3; i++, reg_addr += 4, params += 2)
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reg_write(ispbase, reg_addr, CREATE_REG_VALUE(u16, params, 2, 0xfff, 16));
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reg_write(ispbase, reg_addr, CREATE_REG_VALUE(u16, &setting->hue_info.cos, 2, 0x3ff, 16));
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@@ -597,7 +597,7 @@ static int isp_set_ctrl_sat(struct stf_i
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reg_write(ispbase, reg_addr, CREATE_REG_VALUE(u16, params, 2, 0x3fff, 16));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -609,7 +609,7 @@ static int isp_set_ctrl_shrp(struct stf_
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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s32 i;
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-
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+
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for(i = 0; i < 4; i++, reg_addr += 4)
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reg_write(ispbase, reg_addr, ((u32)(setting->strength.diff[i] & 0x3ff) << 16) | ((u32)(setting->weight.weight[i] & 0xf) << 8));
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FILL_ISP_REGS(u8, ispbase, reg_addr, (u8 *)(&setting->weight.weight[4]), 15 - 4, 0xf, 8);
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@@ -622,7 +622,7 @@ static int isp_set_ctrl_shrp(struct stf_
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reg_write(ispbase, reg_addr, ((u32)(setting->pdirf & 0xf) << 28) | ((u32)(setting->ndirf & 0xf) << 24) | (setting->weight.recip_wei_sum & 0x3fffff));
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -633,11 +633,11 @@ static int isp_set_ctrl_ycrv(struct stf_
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u32 reg_addr = reg_info->cfg_reg;
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struct stf_vin_dev *vin = isp_dev->stfcamss->vin;
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void __iomem *ispbase = vin->isp_base;
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-
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+
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FILL_ISP_REGS(u16, ispbase, reg_addr, (u16 *)(setting->curve.y), 64, 0x3ff, 0);
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reg_set_bit(ispbase, reg_info->en_reg, 1 << reg_info->en_nbit, setting->enabled ? 1 << reg_info->en_nbit : 0);
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-
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+
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return 0;
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}
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@@ -661,11 +661,11 @@ static int isp_set_ctrl_sc(struct stf_is
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reg_write(ispbase, 0xb8, ((u32)(setting->crop_config.v_start) << 16) | setting->crop_config.h_start);
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// SC config1
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- reg_write(ispbase, 0xbc, ((u32)(setting->awb_config.sel) << 30) | ((u32)(setting->awb_config.awb_ps_grb_ba) << 16) |
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+ reg_write(ispbase, 0xbc, ((u32)(setting->awb_config.sel) << 30) | ((u32)(setting->awb_config.awb_ps_grb_ba) << 16) |
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((u32)(setting->crop_config.sw_height) << 8) | setting->crop_config.sw_width);
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// SC decimation config
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- reg_write(ispbase, 0xd8, ((u32)(setting->crop_config.vkeep) << 24) | ((u32)(setting->crop_config.vperiod) << 16) |
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+ reg_write(ispbase, 0xd8, ((u32)(setting->crop_config.vkeep) << 24) | ((u32)(setting->crop_config.vperiod) << 16) |
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((u32)(setting->crop_config.hkeep) << 8) | setting->crop_config.hperiod);
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// SC AWB pixel sum config
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@@ -676,7 +676,7 @@ static int isp_set_ctrl_sc(struct stf_is
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reg_write(ispbase, 0xd4, CREATE_REG_VALUE(u16, &setting->awb_config.ws_ps_config.awb_ps_grbl, 2, 0xffff, 16));
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// AF register
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- reg_write(ispbase, 0xc0,
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+ reg_write(ispbase, 0xc0,
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((u32)(setting->af_config.es_hor_thr & 0x1ff) << 16) |
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((u32)(setting->af_config.es_ver_thr & 0xff) << 8) |
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((setting->af_config.ver_en & 0x1) << 3) |
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@@ -1217,7 +1217,7 @@ static int isp_get_interface_type(struct
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static int isp_set_stream(struct v4l2_subdev *sd, int enable)
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{
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struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd);
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- int ret = 0, interface_type;
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+ int interface_type;
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struct v4l2_mbus_framefmt *fmt;
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struct v4l2_event src_ch = { 0 };
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@@ -1225,6 +1225,7 @@ static int isp_set_stream(struct v4l2_su
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mutex_lock(&isp_dev->stream_lock);
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if (enable) {
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if (isp_dev->stream_count == 0) {
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+ v4l2_ctrl_handler_setup(&isp_dev->ctrls.handler);
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isp_dev->hw_ops->isp_clk_enable(isp_dev);
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if (!user_config_isp)
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isp_dev->hw_ops->isp_config_set(isp_dev);
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@@ -1256,15 +1257,7 @@ static int isp_set_stream(struct v4l2_su
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exit:
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mutex_unlock(&isp_dev->stream_lock);
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- mutex_lock(&isp_dev->power_lock);
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- /* restore controls */
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- if (enable && isp_dev->power_count == 1) {
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- mutex_unlock(&isp_dev->power_lock);
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- ret = v4l2_ctrl_handler_setup(&isp_dev->ctrls.handler);
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- } else
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- mutex_unlock(&isp_dev->power_lock);
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-
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- return ret;
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+ return 0;
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}
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/*Try to match sensor format with sink, and then get the index as default.*/
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