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https://github.com/openwrt/openwrt.git
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0a4b309f41
Backport initial LEDs hw control support. Currently this is limited to only rx/tx and link events for the netdev trigger but the API got accepted and the additional modes are working on and will be backported later. Refresh every patch and add the additional config flag for QCA8K new LEDs support. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
83 lines
2.9 KiB
Diff
83 lines
2.9 KiB
Diff
From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Mon, 13 Feb 2023 02:33:14 +0000
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Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
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Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
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PHYs which require calibration data from the SoC's efuse.
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Despite the similar design the driver doesn't share any code with the
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existing mediatek-ge.c, so add support for these PHYs by introducing a
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new driver for only MediaTek's ARM64 SoCs.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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MAINTAINERS | 9 +
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drivers/net/phy/Kconfig | 12 +
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++
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drivers/net/phy/mediatek-ge.c | 3 +-
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5 files changed, 1287 insertions(+), 1 deletion(-)
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create mode 100644 drivers/net/phy/mediatek-ge-soc.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -11797,6 +11797,15 @@ S: Maintained
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F: drivers/net/pcs/pcs-mtk-lynxi.c
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F: include/linux/pcs/pcs-mtk-lynxi.h
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+MEDIATEK ETHERNET PHY DRIVERS
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+M: Daniel Golle <daniel@makrotopia.org>
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+M: Qingfang Deng <dqfext@gmail.com>
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+M: SkyLake Huang <SkyLake.Huang@mediatek.com>
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+L: netdev@vger.kernel.org
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+S: Maintained
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+F: drivers/net/phy/mediatek-ge-soc.c
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+F: drivers/net/phy/mediatek-ge.c
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+
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MEDIATEK I2C CONTROLLER DRIVER
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M: Qii Wang <qii.wang@mediatek.com>
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L: linux-i2c@vger.kernel.org
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY
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help
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Supports the MediaTek Gigabit Ethernet PHYs.
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+config MEDIATEK_GE_SOC_PHY
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+ tristate "MediaTek SoC Ethernet PHYs"
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+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
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+ select NVMEM_MTK_EFUSE
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+ help
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+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
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+
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+ Include support for built-in Ethernet PHYs which are present in
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+ the MT7981 and MT7988 SoCs. These PHYs need calibration data
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+ present in the SoCs efuse and will dynamically calibrate VCM
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+ (common-mode voltage) during startup.
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+
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config MICREL_PHY
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tristate "Micrel PHYs"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
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obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
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obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
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obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
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+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
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obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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--- a/drivers/net/phy/mediatek-ge.c
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+++ b/drivers/net/phy/mediatek-ge.c
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@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
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module_phy_driver(mtk_gephy_driver);
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static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
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- { PHY_ID_MATCH_VENDOR(0x03a29400) },
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+ { PHY_ID_MATCH_EXACT(0x03a29441) },
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+ { PHY_ID_MATCH_EXACT(0x03a29412) },
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{ }
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};
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