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0e5d67d483
Backport kernel patches for LS1043A Rev1.1 support from upstream, patchwork, and SDK. And update to latest u-boot to support LS1043A Rev1.1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
119 lines
3.8 KiB
Diff
119 lines
3.8 KiB
Diff
From 1569c166572f9576c6726472b5a726a1a56900bd Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Thu, 16 Feb 2017 18:00:14 +0800
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Subject: [PATCH] arm64: dts: ls1046a: update MSI dts node
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Update MSI dts node according to below patchwork patch.
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arm64: dts: ls1046a: add MSI dts node
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https://patchwork.kernel.org/patch/9520299
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 58 +++++++++++++-------------
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1 file changed, 30 insertions(+), 28 deletions(-)
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diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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index 179c38b..f96be34 100644
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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@@ -44,6 +44,8 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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/ {
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compatible = "fsl,ls1046a";
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interrupt-parent = <&gic>;
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@@ -870,34 +872,34 @@
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big-endian;
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};
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- msi: msi-controller@1580000 {
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+ msi1: msi-controller@1580000 {
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compatible = "fsl,ls1046a-msi";
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- #address-cells = <2>;
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- #size-cells = <2>;
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- ranges;
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msi-controller;
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+ reg = <0x0 0x1580000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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- msi-bank@1580000 {
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- reg = <0x0 0x1580000 0x0 0x10000>;
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- interrupts = <0 116 0x4>,
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- <0 111 0x4>,
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- <0 112 0x4>,
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- <0 113 0x4>;
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- };
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- msi-bank@1590000 {
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- reg = <0x0 0x1590000 0x0 0x10000>;
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- interrupts = <0 126 0x4>,
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- <0 121 0x4>,
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- <0 122 0x4>,
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- <0 123 0x4>;
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- };
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- msi-bank@15a0000 {
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- reg = <0x0 0x15a0000 0x0 0x10000>;
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- interrupts = <0 160 0x4>,
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- <0 155 0x4>,
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- <0 156 0x4>,
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- <0 157 0x4>;
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- };
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+ msi2: msi-controller@1590000 {
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+ compatible = "fsl,ls1046a-msi";
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+ msi-controller;
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+ reg = <0x0 0x1590000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ msi3: msi-controller@15a0000 {
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+ compatible = "fsl,ls1046a-msi";
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+ msi-controller;
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+ reg = <0x0 0x15a0000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie@3400000 {
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@@ -916,7 +918,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
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@@ -941,7 +943,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
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@@ -966,7 +968,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
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--
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2.1.0.27.g96db324
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