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bb1eb5e8e6
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang@ieiworld.com>
(cherry picked from commit c98ddf0f01)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
103 lines
2.5 KiB
Diff
103 lines
2.5 KiB
Diff
From cbafcad0641e99831ff7c57ac8f79aed502f33e5 Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 4 Oct 2019 16:27:24 +0200
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Subject: [PATCH] arm64: dts: marvell: Add support for AP807/AP807-quad
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Describe AP807 and AP807-quad support.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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.../boot/dts/marvell/armada-ap807-quad.dtsi | 51 +++++++++++++++++++
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arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 29 +++++++++++
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2 files changed, 80 insertions(+)
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create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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@@ -0,0 +1,51 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree file for Marvell Armada AP807 Quad
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+ *
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+ * Copyright (C) 2019 Marvell Technology Group Ltd.
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+ */
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+
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+#include "armada-ap807.dtsi"
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+
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+/ {
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+ model = "Marvell Armada AP807 Quad";
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+ compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72", "arm,armv8";
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+ reg = <0x000>;
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+ enable-method = "psci";
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+ #cooling-cells = <2>;
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+ clocks = <&cpu_clk 0>;
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+ };
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72", "arm,armv8";
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+ reg = <0x001>;
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+ enable-method = "psci";
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+ #cooling-cells = <2>;
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+ clocks = <&cpu_clk 0>;
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+ };
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+ cpu2: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72", "arm,armv8";
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+ reg = <0x100>;
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+ enable-method = "psci";
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+ #cooling-cells = <2>;
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+ clocks = <&cpu_clk 1>;
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+ };
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+ cpu3: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72", "arm,armv8";
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+ reg = <0x101>;
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+ enable-method = "psci";
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+ #cooling-cells = <2>;
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+ clocks = <&cpu_clk 1>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
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@@ -0,0 +1,29 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree file for Marvell Armada AP807
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+ *
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+ * Copyright (C) 2019 Marvell Technology Group Ltd.
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+ */
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+
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+#define AP_NAME ap807
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+#include "armada-ap80x.dtsi"
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+
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+/ {
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+ model = "Marvell Armada AP807";
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+ compatible = "marvell,armada-ap807";
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+};
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+
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+&ap_syscon0 {
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+ ap_clk: clock {
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+ compatible = "marvell,ap807-clock";
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+ #clock-cells = <1>;
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+ };
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+};
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+
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+&ap_syscon1 {
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+ cpu_clk: clock-cpu {
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+ compatible = "marvell,ap807-cpu-clock";
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+ clocks = <&ap_clk 0>, <&ap_clk 1>;
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+ #clock-cells = <1>;
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+ };
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+};
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