mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
7054721cf9
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.
Where the majority of devices is using it, also move the serial0
alias to the DTSI.
*) Since GL-USB150 even defines serial0 alias, the missing uart
is probably just a mistake. Anyway, disable it for now so this
patch stays cosmetic.
Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
164 lines
3.4 KiB
Plaintext
164 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "ath79.dtsi"
|
|
|
|
/ {
|
|
compatible = "qca,ar7240";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "mips,mips24Kc";
|
|
clocks = <&pll ATH79_CLK_CPU>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
ahb: ahb {
|
|
apb {
|
|
ddr_ctrl: memory-controller@18000000 {
|
|
compatible = "qca,ar9132-ddr-controller",
|
|
"qca,ar7240-ddr-controller";
|
|
reg = <0x18000000 0x100>;
|
|
|
|
#qca,ddr-wb-channel-cells = <1>;
|
|
};
|
|
|
|
uart: uart@18020000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x18020000 0x20>;
|
|
interrupts = <3>;
|
|
|
|
clocks = <&pll ATH79_CLK_AHB>;
|
|
clock-names = "uart";
|
|
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
no-loopback-test;
|
|
};
|
|
|
|
gpio: gpio@18040000 {
|
|
compatible = "qca,ar7240-gpio",
|
|
"qca,ar7100-gpio";
|
|
reg = <0x18040000 0x30>;
|
|
interrupts = <2>;
|
|
|
|
ngpios = <18>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pinmux: pinmux@18040028 {
|
|
compatible = "pinctrl-single";
|
|
|
|
reg = <0x18040028 0x8>;
|
|
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
#pinctrl-cells = <2>;
|
|
|
|
jtag_disable_pins: pinmux_jtag_disable_pins {
|
|
pinctrl-single,bits = <0x0 0x1 0x1>;
|
|
};
|
|
|
|
switch_led_disable_pins: pinmux_switch_led_disable_pins {
|
|
pinctrl-single,bits = <0x0 0x0 0xf8>;
|
|
};
|
|
|
|
clks_disable_pins: pinmux_clks_disable_pins {
|
|
pinctrl-single,bits = <0x0 0x0 0x81f00>;
|
|
};
|
|
};
|
|
|
|
pll: pll-controller@18050000 {
|
|
compatible = "qca,ar7240-pll", "syscon";
|
|
reg = <0x18050000 0x3c>;
|
|
|
|
clock-names = "ref";
|
|
/* The board must provides the ref clock */
|
|
|
|
#clock-cells = <1>;
|
|
clock-output-names = "cpu", "ddr", "ahb";
|
|
};
|
|
|
|
wdt: wdt@18060008 {
|
|
compatible = "qca,ar7130-wdt";
|
|
reg = <0x18060008 0x8>;
|
|
|
|
interrupts = <4>;
|
|
|
|
clocks = <&pll ATH79_CLK_AHB>;
|
|
clock-names = "wdt";
|
|
};
|
|
|
|
rst: reset-controller@1806001c {
|
|
compatible = "qca,ar7240-reset",
|
|
"qca,ar7100-reset";
|
|
reg = <0x1806001c 0x4>;
|
|
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pcie: pcie-controller@180c0000 {
|
|
compatible = "qcom,ar7240-pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x0 0x0>;
|
|
reg = <0x180c0000 0x1000>, /* CRP */
|
|
<0x180f0000 0x100>, /* CTRL */
|
|
<0x14000000 0x1000>; /* CFG */
|
|
reg-names = "crp_base", "ctrl_base", "cfg_base";
|
|
ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
|
|
0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
|
|
resets = <&rst 6>, <&rst 7>;
|
|
reset-names = "hc", "phy";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-map-mask = <0 0 0 1>;
|
|
interrupt-map = <0 0 0 0 &pcie 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spi: spi@1f000000 {
|
|
compatible = "qca,ar7240-spi",
|
|
"qca,ar7100-spi";
|
|
reg = <0x1f000000 0x10>;
|
|
|
|
clocks = <&pll ATH79_CLK_AHB>;
|
|
clock-names = "ahb";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&cpuintc {
|
|
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
|
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
|
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
|
};
|