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Backport lots upstream changes, many of them fixes, for the mt7530 DSA driver. Some of them may or may not find they way into Linux 6.1 stable, some certainly won't because they are fixes for backported commits which aren't even present in Linux 6.1 upstream. Apart from adding new patches, also remove mutated patch 723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch which should never have been added for Linux 6.1 -- it was applied already upstream but coincidentally would fuzzy-apply in the wrong place as well (for MT7530 instead of MT7531). While that didn't really hurt anyone it is just unneeded. The other deleted patch 795-mt7530-register-OF-node-for-internal-MDIO-bus.patch has been replaced by an equivalent commit with a more complete patch description by upstream maintainer Arınç Ünal. The remaining differences compared to the upstream driver are: * C22/C45 MDIO ops aren't split Upstream did that, backporting it would require making changes to *all* DSA drivers * 'slave' -> 'user', 'master' -> 'conduit' language change in DSA * support for selecting preferred CPU port on MT7531 Also this would require too many DSA framework changes potentially affecting other devices. If we ever really use Linux 6.1 in a release (I hope not) we can still reconsider to make the effort to backport that. In addition to some minor bug fixes and style improvements the switch should now behave more conformant when it comes to link-local frames, and we will again be able to cleanly pick patches from upstream. MAINTAIERS NOTE: Three patches are already part of Linux stable and should be removed with the next minor kernel version bump: 789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch 789-STABLE-02-net-dsa-mt7530-fix-link-local-frames-that-ingress-vl.patch 789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch Signed-off-by: Daniel Golle <daniel@makrotopia.org>
75 lines
3.0 KiB
Diff
75 lines
3.0 KiB
Diff
From cfa7c85f92cd3814ad9748eb1ab25658c7f7cc67 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Wed, 20 Mar 2024 23:45:30 +0300
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Subject: [PATCH 48/48] net: dsa: mt7530: fix improper frames on all 25MHz and
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40MHz XTAL MT7530
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The MT7530 switch after reset initialises with a core clock frequency that
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works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
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frequency must be set to 500MHz.
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The mt7530_pll_setup() function is responsible of setting the core clock
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frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
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causes MT7530 switch with 25MHz XTAL to egress and ingress frames
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improperly.
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Introduce a check to run it only on MT7530 with 40MHz XTAL.
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The core clock frequency is set by writing to a switch PHY's register.
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Access to the PHY's register is done via the MDIO bus the switch is also
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on. Therefore, it works only when the switch makes switch PHYs listen on
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the MDIO bus the switch is on. This is controlled either by the state of
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the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
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modifiable trap register.
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When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
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accessing PHY registers via the PHY indirect access control register of the
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switch.
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When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
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accessing PHY registers via the MDIO bus the switch is on.
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For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
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the core clock frequency won't be set to 500MHz, causing the switch to
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egress and ingress frames improperly.
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Run mt7530_pll_setup() after PHY direct access is set on the modifiable
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trap register.
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With these two changes, all MT7530 switches with 25MHz and 40MHz, and
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P1_LED_1 pulled high or low, will egress and ingress frames properly.
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Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
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Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/mt7530.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -2259,8 +2259,6 @@ mt7530_setup(struct dsa_switch *ds)
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SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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SYS_CTRL_REG_RST);
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- mt7530_pll_setup(priv);
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-
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/* Lower Tx driving for TRGMII path */
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for (i = 0; i < NUM_TRGMII_CTRL; i++)
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mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
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@@ -2276,6 +2274,9 @@ mt7530_setup(struct dsa_switch *ds)
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val |= MHWTRAP_MANUAL;
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mt7530_write(priv, MT7530_MHWTRAP, val);
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+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
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+ mt7530_pll_setup(priv);
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+
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mt753x_trap_frames(priv);
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/* Enable and reset MIB counters */
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