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New stm32 target introduces support for stm32mp1 based devices. For now it includes an initial support of the STM32MP135F-DK device. The specifications bellow only list supported features. Specifications -------------- SOC: STM32MP135FAF7 RAM: 512 MiB Storage: SD Card Ethernet: 2x 100 Mbps Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n) LEDs: Heartbeat (Blue) Buttons: 1x Reset, 1x User (USER2) USB: 4x 2.0 Type-A Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://github.com/openwrt/openwrt/pull/16716 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
102 lines
3.4 KiB
Diff
102 lines
3.4 KiB
Diff
From 796669a85c5c4fa80cb8790e9adcccbbd99750e8 Mon Sep 17 00:00:00 2001
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From: Christophe Roullier <christophe.roullier@foss.st.com>
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Date: Tue, 11 Jun 2024 10:36:05 +0200
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Subject: [PATCH 7/8] net: stmmac: dwmac-stm32: Mask support for PMCR
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configuration
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Add possibility to have second argument in syscon property to manage
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mask. This mask will be used to address right BITFIELDS of PMCR register.
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Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
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Reviewed-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 28 +++++++++++++------
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1 file changed, 19 insertions(+), 9 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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@@ -90,6 +90,7 @@ struct stm32_dwmac {
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int eth_ref_clk_sel_reg;
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int irq_pwr_wakeup;
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u32 mode_reg; /* MAC glue-logic mode register */
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+ u32 mode_mask;
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struct regmap *regmap;
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u32 speed;
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const struct stm32_ops *ops;
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@@ -102,8 +103,8 @@ struct stm32_ops {
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void (*resume)(struct stm32_dwmac *dwmac);
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int (*parse_data)(struct stm32_dwmac *dwmac,
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struct device *dev);
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- u32 syscfg_eth_mask;
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bool clk_rx_enable_in_suspend;
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+ u32 syscfg_clr_off;
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};
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static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
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@@ -256,13 +257,16 @@ static int stm32mp1_configure_pmcr(struc
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dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
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+ /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
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+ val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
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+
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/* Need to update PMCCLRR (clear register) */
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- regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
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- dwmac->ops->syscfg_eth_mask);
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+ regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
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+ dwmac->mode_mask);
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/* Update PMCSETR (set register) */
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return regmap_update_bits(dwmac->regmap, reg,
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- dwmac->ops->syscfg_eth_mask, val);
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+ dwmac->mode_mask, val);
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}
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static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
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@@ -303,7 +307,7 @@ static int stm32mcu_set_mode(struct plat
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dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
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return regmap_update_bits(dwmac->regmap, reg,
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- dwmac->ops->syscfg_eth_mask, val << 23);
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+ SYSCFG_MCU_ETH_MASK, val << 23);
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}
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static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
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@@ -348,8 +352,15 @@ static int stm32_dwmac_parse_data(struct
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return PTR_ERR(dwmac->regmap);
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err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
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- if (err)
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+ if (err) {
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dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
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+ return err;
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+ }
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+
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+ dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
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+ err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
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+ if (err)
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+ dev_dbg(dev, "Warning sysconfig register mask not set\n");
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return err;
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}
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@@ -540,8 +551,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_
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stm32_dwmac_suspend, stm32_dwmac_resume);
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static struct stm32_ops stm32mcu_dwmac_data = {
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- .set_mode = stm32mcu_set_mode,
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- .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
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+ .set_mode = stm32mcu_set_mode
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};
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static struct stm32_ops stm32mp1_dwmac_data = {
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@@ -549,7 +559,7 @@ static struct stm32_ops stm32mp1_dwmac_d
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.suspend = stm32mp1_suspend,
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.resume = stm32mp1_resume,
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.parse_data = stm32mp1_parse_data,
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- .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
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+ .syscfg_clr_off = 0x44,
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.clk_rx_enable_in_suspend = true
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};
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