mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 10:39:04 +00:00
24d84a13a4
Manually rebased:
ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch
All other patches automatically rebased.
Signed-off-by: John Audia <therealgraysky@proton.me>
(cherry picked from commit d4aad642ff)
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
From 4ec54ed688271966193b572ba5b150c6a4d270fc Mon Sep 17 00:00:00 2001
|
|
From: Tim Gover <tim.gover@raspberrypi.com>
|
|
Date: Thu, 24 Jun 2021 17:58:05 +0100
|
|
Subject: [PATCH] drm: vc4: Fix pixel-wrap issue with DVP teardown
|
|
|
|
Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
|
|
in an internal, non resettable FIFO within PixelValve when changing
|
|
HDMI resolution.
|
|
|
|
The blank pixels features of the DVP can prevent signals back to
|
|
pixelvalve causing it to not clear the FIFO. Adjust the ordering
|
|
and timing of operations to ensure the clear signal makes it through to
|
|
pixelvalve.
|
|
|
|
Signed-off-by: Tim Gover <tim.gover@raspberrypi.com>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++-------
|
|
1 file changed, 8 insertions(+), 7 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -613,12 +613,12 @@ static void vc4_hdmi_encoder_post_crtc_d
|
|
|
|
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
|
|
- VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
|
|
+ HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL,
|
|
- HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
|
|
+ mdelay(1);
|
|
|
|
+ HDMI_WRITE(HDMI_VID_CTL,
|
|
+ HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
|
|
vc4_hdmi_disable_scrambling(encoder);
|
|
}
|
|
|
|
@@ -628,12 +628,12 @@ static void vc4_hdmi_encoder_post_crtc_p
|
|
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
|
|
int ret;
|
|
|
|
+ HDMI_WRITE(HDMI_VID_CTL,
|
|
+ HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
|
|
+
|
|
if (vc4_hdmi->variant->phy_disable)
|
|
vc4_hdmi->variant->phy_disable(vc4_hdmi);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL,
|
|
- HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
|
|
-
|
|
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
|
|
if (vc4_hdmi->bvb_req)
|
|
clk_request_done(vc4_hdmi->bvb_req);
|
|
@@ -1014,6 +1014,7 @@ static void vc4_hdmi_encoder_post_crtc_e
|
|
|
|
HDMI_WRITE(HDMI_VID_CTL,
|
|
VC4_HD_VID_CTL_ENABLE |
|
|
+ VC4_HD_VID_CTL_CLRRGB |
|
|
VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
|
|
VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
|
|
(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
|