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https://github.com/openwrt/openwrt.git
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9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
115 lines
3.3 KiB
Diff
115 lines
3.3 KiB
Diff
From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:22:43 +0100
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Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
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out of soc init
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Preparation for reusing functions for DT
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
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1 file changed, 17 insertions(+), 21 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
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ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
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ar724x_clk_init(ref_clk, ath79_pll_base);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
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ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ar9330_clk_init(ref_clk, ath79_pll_base);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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-
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iounmap(dpll_base);
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}
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@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca955x_clocks_init(void)
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@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca956x_clocks_init(void)
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@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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void __init ath79_clocks_init(void)
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{
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+ const char *wdt;
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+ const char *uart;
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+
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if (soc_is_ar71xx())
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ar71xx_clocks_init();
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else if (soc_is_ar724x() || soc_is_ar913x())
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@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
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qca956x_clocks_init();
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else
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BUG();
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+
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+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
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+ wdt = "ahb";
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+ uart = "ahb";
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+ } else if (soc_is_ar933x()) {
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+ wdt = "ahb";
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+ uart = "ref";
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+ } else {
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+ wdt = "ref";
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+ uart = "ref";
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+ }
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+
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+ clk_add_alias("wdt", NULL, wdt, NULL);
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+ clk_add_alias("uart", NULL, uart, NULL);
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}
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unsigned long __init
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