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Deleted (upstreamed): bcm27xx/patches-5.10/950-0669-drm-vc4-hdmi-Make-sure-the-device-is-powered-with-CE.patch [1] bcm27xx/patches-5.10/950-0672-drm-vc4-hdmi-Move-initial-register-read-after-pm_run.patch [1] gemini/patches-5.10/0003-ARM-dts-gemini-NAS4220-B-fis-index-block-with-128-Ki.patch [2] Manually rebased: bcm27xx/patches-5.10/950-0675-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-CEC-int.patch Manually reverted: generic/pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch [3] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=55b10b88ac8654fc2f31518aa349a2e643b37f18 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=958a8819d41420d7a74ed922a09cacc0ba3a4218 [3] https://lore.kernel.org/all/trinity-2a727d96-0335-4d03-8f30-e22a0e10112d-1643363480085@3c-app-gmx-bap33/ Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From a1dcaba80910c0196b6e51111ba3890372067e0e Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 2 May 2019 15:11:05 -0700
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Subject: [PATCH] clk: bcm2835: Add support for setting leaf clock
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rates while running.
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As long as you wait for !BUSY, you can do glitch-free updates of clock
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rate while the clock is running.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 22 +++++++++++++---------
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1 file changed, 13 insertions(+), 9 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1110,15 +1110,19 @@ static int bcm2835_clock_set_rate(struct
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spin_lock(&cprman->regs_lock);
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- /*
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- * Setting up frac support
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- *
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- * In principle it is recommended to stop/start the clock first,
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- * but as we set CLK_SET_RATE_GATE during registration of the
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- * clock this requirement should be take care of by the
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- * clk-framework.
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+ ctl = cprman_read(cprman, data->ctl_reg);
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+
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+ /* If the clock is running, we have to pause clock generation while
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+ * updating the control and div regs. This is glitchless (no clock
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+ * signals generated faster than the rate) but each reg access is two
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+ * OSC cycles so the clock will slow down for a moment.
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*/
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- ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
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+ if (ctl & CM_ENABLE) {
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+ cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE);
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+ bcm2835_clock_wait_busy(clock);
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+ }
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+
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+ ctl &= ~CM_FRAC;
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ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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cprman_write(cprman, data->ctl_reg, ctl);
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@@ -1494,7 +1498,7 @@ static struct clk_hw *bcm2835_register_c
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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init.ops = &bcm2835_clock_clk_ops;
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- init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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+ init.flags |= CLK_SET_PARENT_GATE;
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/* If the clock wasn't actually enabled at boot, it's not
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* critical.
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