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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
173 lines
4.3 KiB
Diff
173 lines
4.3 KiB
Diff
From 3411a9a1be9a8d8fef236a81edbce2a1a8218a32 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Mon, 16 May 2022 00:16:48 -0500
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Subject: [PATCH 31/90] mtd: nand: sunxi: Convert to the driver model
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Clocks, resets, and pinmuxes are now handled by the driver model, so the
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only thing the "board" code needs to do is load the driver. This matches
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the pattern used by other DM raw NAND drivers (there is no NAND uclass).
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The actual board code is now only needed in SPL.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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board/sunxi/board.c | 5 +-
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drivers/mtd/nand/raw/sunxi_nand.c | 81 ++++++++++++++++++-------------
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2 files changed, 49 insertions(+), 37 deletions(-)
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--- a/board/sunxi/board.c
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+++ b/board/sunxi/board.c
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@@ -311,7 +311,7 @@ int dram_init(void)
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return 0;
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}
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-#if defined(CONFIG_NAND_SUNXI)
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+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
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static void nand_pinmux_setup(void)
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{
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unsigned int pin;
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@@ -347,9 +347,6 @@ void board_nand_init(void)
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{
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nand_pinmux_setup();
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nand_clock_setup();
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-#ifndef CONFIG_SPL_BUILD
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- sunxi_nand_init();
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-#endif
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}
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#endif /* CONFIG_NAND_SUNXI */
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--- a/drivers/mtd/nand/raw/sunxi_nand.c
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+++ b/drivers/mtd/nand/raw/sunxi_nand.c
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@@ -24,11 +24,13 @@
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* GNU General Public License for more details.
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*/
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+#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <nand.h>
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+#include <reset.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <linux/bitops.h>
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@@ -260,7 +262,7 @@ static inline struct sunxi_nand_chip *to
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* NAND Controller structure: stores sunxi NAND controller information
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*
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* @controller: base controller structure
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- * @dev: parent device (used to print error messages)
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+ * @dev: DM device (used to print error messages)
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* @regs: NAND controller registers
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* @ahb_clk: NAND Controller AHB clock
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* @mod_clk: NAND Controller mod clock
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@@ -273,7 +275,7 @@ static inline struct sunxi_nand_chip *to
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*/
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struct sunxi_nfc {
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struct nand_hw_control controller;
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- struct device *dev;
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+ struct udevice *dev;
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void __iomem *regs;
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struct clk *ahb_clk;
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struct clk *mod_clk;
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@@ -1772,54 +1774,67 @@ static void sunxi_nand_chips_cleanup(str
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}
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#endif /* __UBOOT__ */
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-void sunxi_nand_init(void)
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+static int sunxi_nand_probe(struct udevice *dev)
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{
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- struct sunxi_nfc *nfc;
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- phys_addr_t regs;
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- ofnode node;
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+ struct sunxi_nfc *nfc = dev_get_priv(dev);
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+ struct reset_ctl_bulk rst_bulk;
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+ struct clk_bulk clk_bulk;
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int ret;
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- nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
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- if (!nfc)
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- return;
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-
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+ nfc->dev = dev;
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spin_lock_init(&nfc->controller.lock);
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init_waitqueue_head(&nfc->controller.wq);
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INIT_LIST_HEAD(&nfc->chips);
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- node = ofnode_by_compatible(ofnode_null(), "allwinner,sun4i-a10-nand");
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- if (!ofnode_valid(node)) {
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- pr_err("unable to find nfc node in device tree\n");
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- goto err;
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- }
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-
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- if (!ofnode_is_enabled(node)) {
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- pr_err("nfc disabled in device tree\n");
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- goto err;
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- }
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-
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- regs = ofnode_get_addr(node);
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- if (regs == FDT_ADDR_T_NONE) {
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- pr_err("unable to find nfc address in device tree\n");
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- goto err;
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- }
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+ nfc->regs = dev_read_addr_ptr(dev);
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+ if (!nfc->regs)
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+ return -EINVAL;
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- nfc->regs = (void *)regs;
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+ ret = reset_get_bulk(dev, &rst_bulk);
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+ if (!ret)
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+ reset_deassert_bulk(&rst_bulk);
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+
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+ ret = clk_get_bulk(dev, &clk_bulk);
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+ if (!ret)
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+ clk_enable_bulk(&clk_bulk);
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ret = sunxi_nfc_rst(nfc);
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if (ret)
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- goto err;
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+ return ret;
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- ret = sunxi_nand_chips_init(node, nfc);
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+ ret = sunxi_nand_chips_init(dev_ofnode(dev), nfc);
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if (ret) {
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- dev_err(nfc->dev, "failed to init nand chips\n");
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- goto err;
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+ dev_err(dev, "failed to init nand chips\n");
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+ return ret;
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}
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- return;
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+ return 0;
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+}
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-err:
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- kfree(nfc);
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+static const struct udevice_id sunxi_nand_ids[] = {
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+ {
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+ .compatible = "allwinner,sun4i-a10-nand",
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+ },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(sunxi_nand) = {
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+ .name = "sunxi_nand",
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+ .id = UCLASS_MTD,
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+ .of_match = sunxi_nand_ids,
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+ .probe = sunxi_nand_probe,
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+ .priv_auto = sizeof(struct sunxi_nfc),
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+};
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+
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+void board_nand_init(void)
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+{
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+ struct udevice *dev;
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+ int ret;
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MTD,
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+ DM_DRIVER_GET(sunxi_nand), &dev);
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+ if (ret && ret != -ENODEV)
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+ pr_err("Failed to initialize sunxi NAND controller: %d\n", ret);
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}
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MODULE_LICENSE("GPL v2");
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