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fdb563c1a5
Recently added PCS patch requires a refresh, so lets do it. Signed-off-by: Robert Marko <robimarko@gmail.com>
136 lines
4.6 KiB
Diff
136 lines
4.6 KiB
Diff
From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 12 Feb 2024 14:23:04 +0200
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Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018
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When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second
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PHY port would overlap with one used by SGMII+ port. SoC has register
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to select different PCS in such case.
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Original code used PHY_ID for this decision, which also had other
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issues, but is no longer viable since we moved to upstream QCA807x
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driver.
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Introduce DT property port3_pcs_channel to allow describing this in DT.
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Default value is <2>, and for some QCA8072 designs <4> would be needed.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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include/init/ssdk_dts.h | 2 ++
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src/adpt/cppe/adpt_cppe_portctrl.c | 4 ++--
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src/adpt/hppe/adpt_hppe_uniphy.c | 7 +------
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src/init/ssdk_dts.c | 27 +++++++++++++++++++++++++++
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4 files changed, 32 insertions(+), 8 deletions(-)
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--- a/include/init/ssdk_dts.h
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+++ b/include/init/ssdk_dts.h
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@@ -101,6 +101,7 @@ typedef struct
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a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
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a_uint32_t clk_mode;
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a_uint32_t pcie_hw_base;
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+ a_uint32_t port3_pcs_channel;
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} ssdk_dt_cfg;
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#define SSDK_MAX_NR_ETH 6
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@@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
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struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
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struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
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struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
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+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id);
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int ssdk_switch_device_num_init(void);
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void ssdk_switch_device_num_exit(void);
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--- a/src/adpt/cppe/adpt_cppe_portctrl.c
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+++ b/src/adpt/cppe/adpt_cppe_portctrl.c
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@@ -33,6 +33,7 @@
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#include "hsl_phy.h"
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#include "hsl_port_prop.h"
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#include "hppe_init.h"
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+#include "ssdk_dts.h"
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#include "adpt.h"
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#include "adpt_hppe.h"
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#include "adpt_cppe_portctrl.h"
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@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t d
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case SSDK_PHYSICAL_PORT3:
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case SSDK_PHYSICAL_PORT4:
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if (mode0 == PORT_WRAPPER_PSGMII) {
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- if (hsl_port_phyid_get(dev_id,
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- SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
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+ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
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cppe_port_mux_ctrl.bf.port3_pcs_sel =
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CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
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cppe_port_mux_ctrl.bf.port4_pcs_sel =
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--- a/src/adpt/hppe/adpt_hppe_uniphy.c
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+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
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@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
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{
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a_uint32_t i;
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sw_error_t rv = SW_OK;
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-#if defined(CPPE)
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- a_uint32_t phy_type = 0;
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-#endif
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union uniphy_mode_ctrl_u uniphy_mode_ctrl;
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@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
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SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
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#if defined(CPPE)
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if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
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- phy_type = hsl_port_phyid_get(dev_id,
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- SSDK_PHYSICAL_PORT3);
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- if (phy_type == MALIBU2PORT_PHY) {
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+ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
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SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
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rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
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PORT_WRAPPER_PSGMII);
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--- a/src/init/ssdk_dts.c
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+++ b/src/init/ssdk_dts.c
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@@ -272,6 +272,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32
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return cfg->cmnblk_clk;
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}
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+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
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+{
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+ ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
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+
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+ return cfg->port3_pcs_channel;
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+}
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+
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#ifndef BOARD_AR71XX
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#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
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static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
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@@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
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return;
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}
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+
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+static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id,
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+ struct device_node *switch_node, ssdk_init_cfg *cfg)
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+{
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+ const __be32 *port3_pcs_channel;
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+ a_uint32_t len = 0;
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+
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+ port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
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+ if (!port3_pcs_channel) {
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+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
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+ }
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+ else {
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+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel =
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+ be32_to_cpup(port3_pcs_channel);
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+ }
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+
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+ return;
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+}
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+
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#ifdef IN_UNIPHY
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static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
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{
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@@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
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rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
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SW_RTN_ON_ERROR(rv);
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ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
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+ ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg);
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ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
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ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
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ssdk_dt_parse_interrupt(*dev_id, switch_node);
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