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080691d7b1
Backport Aardvark PCIe controller driver changes that fix MSI support, that were recently sent to the linux-pci mailing list [1]. These changes fix MSI and MSI-X support for this PCIe controller, which, among other things, make it possible to use NVMe drives with this PCIe controllers. [1] https://lore.kernel.org/linux-pci/20220110015018.26359-1-kabel@kernel.org/ Signed-off-by: Marek Behún <kabel@kernel.org>
50 lines
1.8 KiB
Diff
50 lines
1.8 KiB
Diff
From 98feaf97bc64fc640a6c5b1394cd18fc7cd7dac8 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Sun, 28 Mar 2021 14:34:49 +0200
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Subject: [PATCH] PCI: aardvark: Refactor unmasking summary MSI interrupt
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Refactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt
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so that it corresponds to the comments:
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- first mask all ISR0/1
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- then unmask all MSIs
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- then unmask summary MSI interrupt
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 10 ++++++----
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1 file changed, 6 insertions(+), 4 deletions(-)
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diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
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index e641ad566488..5c887772fa97 100644
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -578,15 +578,17 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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/* Disable All ISR0/1 Sources */
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- reg = PCIE_ISR0_ALL_MASK;
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- reg &= ~PCIE_ISR0_MSI_INT_PENDING;
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- advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
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-
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+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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/* Unmask all MSIs */
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advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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+ /* Unmask summary MSI interrupt */
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+ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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+ reg &= ~PCIE_ISR0_MSI_INT_PENDING;
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+ advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
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+
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/* Enable summary interrupt for GIC SPI source */
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reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
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advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
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--
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2.34.1
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