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78858e5d6c
In the past few years, we have received several reports about SPI
Flash not working properly. This is caused by excessively fast
clock frequency. It's really annoying to fix them one by one. Let's
reduce these aggressive frequencies to 50 MHz. This is a safe and
suggested value in the vendor SDK.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 73eeac49be)
Link: https://github.com/openwrt/openwrt/pull/15919
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
142 lines
2.2 KiB
Plaintext
142 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7628an.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Motorola MWR03";
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compatible = "motorola,mwr03", "mediatek,mt7628an-soc";
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aliases {
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led-boot = &led_status_orange;
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led-failsafe = &led_status_orange;
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led-running = &led_status_white;
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led-upgrade = &led_status_orange;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status_orange: status_orange {
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label = "orange:status";
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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};
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led_status_white: status_white {
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label = "white:status";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "config";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "i2s";
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function = "gpio";
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};
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};
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&usbphy {
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status = "disabled";
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};
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&ehci {
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status = "disabled";
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};
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&ohci {
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status = "disabled";
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};
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ðernet {
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nvmem-cells = <&macaddr_factory_4>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <(-1)>;
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};
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&esw {
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mediatek,portmap = <0x3e>;
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mediatek,portdisable = <0x30>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&wmac {
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status = "okay";
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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};
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