openwrt/target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi
Shiji Yang 78858e5d6c ramips: limit max spi clock frequency to 50 MHz
In the past few years, we have received several reports about SPI
Flash not working properly. This is caused by excessively fast
clock frequency. It's really annoying to fix them one by one. Let's
reduce these aggressive frequencies to 50 MHz. This is a safe and
suggested value in the vendor SDK.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 73eeac49be)
Link: https://github.com/openwrt/openwrt/pull/15919
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-07-10 23:41:15 +02:00

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1.7 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7628an.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "hiwifi,hc5x61a", "mediatek,mt7628an-soc";
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "hw_panic";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0xf70000>;
};
partition@fc0000 {
label = "oem";
reg = <0xfc0000 0x20000>;
read-only;
};
bdinfo: partition@fe0000 {
label = "bdinfo";
reg = <0xfe0000 0x10000>;
read-only;
};
partition@ff0000 {
label = "backup";
reg = <0xff0000 0x10000>;
read-only;
};
};
};
};
&ethernet {
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
};
&wmac {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
};