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78858e5d6c
In the past few years, we have received several reports about SPI
Flash not working properly. This is caused by excessively fast
clock frequency. It's really annoying to fix them one by one. Let's
reduce these aggressive frequencies to 50 MHz. This is a safe and
suggested value in the vendor SDK.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 73eeac49be)
Link: https://github.com/openwrt/openwrt/pull/15919
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
189 lines
2.9 KiB
Plaintext
189 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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led-boot = &led_cpu;
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led-failsafe = &led_cpu;
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led-running = &led_cpu;
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led-upgrade = &led_cpu;
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label-mac-device = &gmac0;
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};
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leds {
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compatible = "gpio-leds";
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usb {
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label = "blue:usb";
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gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
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trigger-sources = <&xhci_ehci_port1>;
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linux,default-trigger = "usbport";
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};
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wlan5g {
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label = "blue:wlan5g";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0radio";
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};
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wlan2g {
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label = "blue:wlan2g";
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1radio";
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};
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led_cpu: cpu {
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label = "blue:cpu";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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uboot: partition@0 {
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label = "u-boot";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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label = "config";
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reg = <0x20000 0x10000>;
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read-only;
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};
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factory: partition@30000 {
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label = "factory";
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reg = <0x30000 0x10000>;
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read-only;
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};
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partition@40000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x40000 0xfc0000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "uart3", "jtag", "wdt";
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function = "gpio";
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_uboot_1fc20>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy0>;
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nvmem-cells = <&macaddr_uboot_1fc40>;
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nvmem-cell-names = "mac-address";
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};
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&mdio {
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan1";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan3";
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};
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port@4 {
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status = "okay";
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label = "lan4";
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&uboot {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_uboot_1fc20: macaddr@1fc20 {
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reg = <0x1fc20 0x6>;
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};
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macaddr_uboot_1fc40: macaddr@1fc40 {
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reg = <0x1fc40 0x6>;
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};
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};
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