openwrt/target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi
Shiji Yang 78858e5d6c ramips: limit max spi clock frequency to 50 MHz
In the past few years, we have received several reports about SPI
Flash not working properly. This is caused by excessively fast
clock frequency. It's really annoying to fix them one by one. Let's
reduce these aggressive frequencies to 50 MHz. This is a safe and
suggested value in the vendor SDK.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 73eeac49be)
Link: https://github.com/openwrt/openwrt/pull/15919
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-07-10 23:41:15 +02:00

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#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &ethernet;
};
leds {
compatible = "gpio-leds";
led_wlan: wlan {
label = "blue:wlan";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
usb {
label = "blue:usb";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
led_power: power {
label = "blue:power";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
firmware: partition@50000 {
compatible = "openwrt,uimage", "denx,uimage";
label = "firmware";
openwrt,ih-magic = <0x12291000>;
/* reg property is set based on flash size in DTS files */
};
};
};
};
&state_default {
default {
groups = "i2c", "rgmii1", "wled";
function = "gpio";
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
nvmem-cells = <&macaddr_factory_28>;
nvmem-cell-names = "mac-address";
mediatek,portmap = "llllw";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default", "pa_gpio";
pinctrl-0 = <&pa_pins>;
pinctrl-1 = <&pa_gpio_pins>;
};
&sdhci {
status = "okay";
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_28: macaddr@28 {
reg = <0x28 0x6>;
};
};