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e2448e5e03
This is needed in order to upstream them. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
876 lines
24 KiB
Diff
876 lines
24 KiB
Diff
From 8ec959299a6e4bbdc65d62180aa952ae04cdcf07 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Fri, 24 Jun 2016 22:19:12 +0200
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Subject: [PATCH 10/12] pinctrl: add a pincontrol driver for BCM63268
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs
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to different functions. Depending on the mux, these are either single
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pin configurations or whole pin groups.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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drivers/pinctrl/bcm/Kconfig | 11 +
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drivers/pinctrl/bcm/Makefile | 1 +
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drivers/pinctrl/bcm/pinctrl-bcm63268.c | 821 +++++++++++++++++++++++++
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3 files changed, 833 insertions(+)
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create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63268.c
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--- a/drivers/pinctrl/bcm/Kconfig
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+++ b/drivers/pinctrl/bcm/Kconfig
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@@ -73,6 +73,17 @@ config PINCTRL_BCM6368
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help
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Say Y here to enable the Broadcom BCM6368 GPIO driver.
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+config PINCTRL_BCM63268
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+ bool "Broadcom BCM63268 GPIO driver"
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+ depends on OF_GPIO && (BMIPS_GENERIC || COMPILE_TEST)
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+ select PINMUX
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+ select PINCONF
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+ select GENERIC_PINCONF
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+ select MFD_SYSCON
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+ default BMIPS_GENERIC
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+ help
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+ Say Y here to enable the Broadcom BCM63268 GPIO driver.
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+
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config PINCTRL_IPROC_GPIO
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bool "Broadcom iProc GPIO (with PINCONF) driver"
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depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
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--- a/drivers/pinctrl/bcm/Makefile
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+++ b/drivers/pinctrl/bcm/Makefile
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@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_BCM6328) += pinctr
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obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
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obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
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obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
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+obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
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obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
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obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
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obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
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--- /dev/null
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+++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c
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@@ -0,0 +1,821 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Driver for BCM63268 GPIO unit (pinctrl + GPIO)
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+ *
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+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
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+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
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+ */
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+
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+#include <linux/bitops.h>
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+#include <linux/gpio.h>
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+#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/of.h>
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+#include <linux/of_gpio.h>
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+#include <linux/of_irq.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+
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+#include <linux/pinctrl/machine.h>
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+#include <linux/pinctrl/pinconf.h>
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+#include <linux/pinctrl/pinconf-generic.h>
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+#include <linux/pinctrl/pinmux.h>
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+
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+#include "../core.h"
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+#include "../pinctrl-utils.h"
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+
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+#define MODULE_NAME "bcm63268-pinctrl"
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+#define BCM63268_NUM_GPIOS 52
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+#define BCM63268_NUM_LEDS 24
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+
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+#define BANK_SIZE sizeof(uint32_t)
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+#define PINS_PER_BANK (BANK_SIZE * BITS_PER_BYTE)
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+
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+#define BCM63268_DIROUT_REG 0x04
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+#define BCM63268_DATA_REG 0x0c
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+#define BCM63268_LED_REG 0x10
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+#define BCM63268_MODE_REG 0x18
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+#define BCM63268_CTRL_REG 0x1c
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+#define BCM63268_BASEMODE_REG 0x38
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+#define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */
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+#define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */
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+#define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */
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+#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */
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+#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */
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+#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */
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+#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */
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+
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+enum bcm63268_pinctrl_reg {
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+ BCM63268_LEDCTRL,
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+ BCM63268_MODE,
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+ BCM63268_CTRL,
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+ BCM63268_BASEMODE,
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+};
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+
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+struct bcm63268_pingroup {
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+ const char *name;
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+ const unsigned * const pins;
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+ const unsigned num_pins;
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+};
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+
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+struct bcm63268_function {
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+ const char *name;
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+ const char * const *groups;
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+ const unsigned num_groups;
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+
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+ enum bcm63268_pinctrl_reg reg;
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+ uint32_t mask;
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+};
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+
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+struct bcm63268_pinctrl {
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+ struct device *dev;
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+ struct regmap *regs;
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+
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+ struct pinctrl_dev *pctl_dev;
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+ struct gpio_chip gpio_chip;
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+ struct pinctrl_desc pctl_desc;
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+ struct pinctrl_gpio_range gpio_range;
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+};
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+
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+#define BCM63268_PIN(a, b, basemode) \
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+ { \
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+ .number = a, \
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+ .name = b, \
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+ .drv_data = (void *)(basemode) \
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+ }
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+
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+static const struct pinctrl_pin_desc bcm63268_pins[] = {
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+ PINCTRL_PIN(0, "gpio0"),
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+ PINCTRL_PIN(1, "gpio1"),
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+ BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
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+ BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
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+ BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
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+ BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
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+ BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
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+ BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
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+ PINCTRL_PIN(14, "gpio14"),
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+ PINCTRL_PIN(15, "gpio15"),
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+ PINCTRL_PIN(16, "gpio16"),
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+ PINCTRL_PIN(17, "gpio17"),
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+ PINCTRL_PIN(18, "gpio18"),
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+ PINCTRL_PIN(19, "gpio19"),
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+ PINCTRL_PIN(20, "gpio20"),
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+ PINCTRL_PIN(21, "gpio21"),
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+ PINCTRL_PIN(22, "gpio22"),
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+ PINCTRL_PIN(23, "gpio23"),
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+ BCM63268_PIN(24, "gpio24",
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+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
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+ BCM63268_PIN(25, "gpio25",
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+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
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+ BCM63268_PIN(26, "gpio26",
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+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
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+ BCM63268_PIN(27, "gpio27",
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+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
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+ BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
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+ BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
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+ PINCTRL_PIN(32, "gpio32"),
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+ PINCTRL_PIN(33, "gpio33"),
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+ PINCTRL_PIN(34, "gpio34"),
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+ PINCTRL_PIN(35, "gpio35"),
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+ PINCTRL_PIN(36, "gpio36"),
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+ PINCTRL_PIN(37, "gpio37"),
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+ PINCTRL_PIN(38, "gpio38"),
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+ PINCTRL_PIN(39, "gpio39"),
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+ PINCTRL_PIN(40, "gpio40"),
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+ PINCTRL_PIN(41, "gpio41"),
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+ PINCTRL_PIN(42, "gpio42"),
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+ PINCTRL_PIN(43, "gpio43"),
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+ PINCTRL_PIN(44, "gpio44"),
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+ PINCTRL_PIN(45, "gpio45"),
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+ PINCTRL_PIN(46, "gpio46"),
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+ PINCTRL_PIN(47, "gpio47"),
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+ PINCTRL_PIN(48, "gpio48"),
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+ PINCTRL_PIN(49, "gpio49"),
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+ PINCTRL_PIN(50, "gpio50"),
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+ PINCTRL_PIN(51, "gpio51"),
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+};
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+
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+static unsigned gpio0_pins[] = { 0 };
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+static unsigned gpio1_pins[] = { 1 };
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+static unsigned gpio2_pins[] = { 2 };
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+static unsigned gpio3_pins[] = { 3 };
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+static unsigned gpio4_pins[] = { 4 };
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+static unsigned gpio5_pins[] = { 5 };
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+static unsigned gpio6_pins[] = { 6 };
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+static unsigned gpio7_pins[] = { 7 };
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+static unsigned gpio8_pins[] = { 8 };
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+static unsigned gpio9_pins[] = { 9 };
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+static unsigned gpio10_pins[] = { 10 };
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+static unsigned gpio11_pins[] = { 11 };
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+static unsigned gpio12_pins[] = { 12 };
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+static unsigned gpio13_pins[] = { 13 };
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+static unsigned gpio14_pins[] = { 14 };
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+static unsigned gpio15_pins[] = { 15 };
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+static unsigned gpio16_pins[] = { 16 };
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+static unsigned gpio17_pins[] = { 17 };
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+static unsigned gpio18_pins[] = { 18 };
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+static unsigned gpio19_pins[] = { 19 };
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+static unsigned gpio20_pins[] = { 20 };
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+static unsigned gpio21_pins[] = { 21 };
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+static unsigned gpio22_pins[] = { 22 };
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+static unsigned gpio23_pins[] = { 23 };
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+static unsigned gpio24_pins[] = { 24 };
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+static unsigned gpio25_pins[] = { 25 };
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+static unsigned gpio26_pins[] = { 26 };
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+static unsigned gpio27_pins[] = { 27 };
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+static unsigned gpio28_pins[] = { 28 };
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+static unsigned gpio29_pins[] = { 29 };
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+static unsigned gpio30_pins[] = { 30 };
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+static unsigned gpio31_pins[] = { 31 };
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+static unsigned gpio32_pins[] = { 32 };
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+static unsigned gpio33_pins[] = { 33 };
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+static unsigned gpio34_pins[] = { 34 };
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+static unsigned gpio35_pins[] = { 35 };
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+static unsigned gpio36_pins[] = { 36 };
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+static unsigned gpio37_pins[] = { 37 };
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+static unsigned gpio38_pins[] = { 38 };
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+static unsigned gpio39_pins[] = { 39 };
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+static unsigned gpio40_pins[] = { 40 };
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+static unsigned gpio41_pins[] = { 41 };
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+static unsigned gpio42_pins[] = { 42 };
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+static unsigned gpio43_pins[] = { 43 };
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+static unsigned gpio44_pins[] = { 44 };
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+static unsigned gpio45_pins[] = { 45 };
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+static unsigned gpio46_pins[] = { 46 };
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+static unsigned gpio47_pins[] = { 47 };
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+static unsigned gpio48_pins[] = { 48 };
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+static unsigned gpio49_pins[] = { 49 };
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+static unsigned gpio50_pins[] = { 50 };
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+static unsigned gpio51_pins[] = { 51 };
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+
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+static unsigned nand_grp_pins[] = {
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+ 2, 3, 4, 5, 6, 7, 24,
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+ 25, 26, 27, 28, 29, 30, 31,
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+};
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+
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+static unsigned dectpd_grp_pins[] = { 8, 9 };
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+static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
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+static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
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+static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
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+static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
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+
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+#define BCM63268_GROUP(n) \
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+ { \
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+ .name = #n, \
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+ .pins = n##_pins, \
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+ .num_pins = ARRAY_SIZE(n##_pins), \
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+ }
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+
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+static struct bcm63268_pingroup bcm63268_groups[] = {
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+ BCM63268_GROUP(gpio0),
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+ BCM63268_GROUP(gpio1),
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+ BCM63268_GROUP(gpio2),
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+ BCM63268_GROUP(gpio3),
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+ BCM63268_GROUP(gpio4),
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+ BCM63268_GROUP(gpio5),
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+ BCM63268_GROUP(gpio6),
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+ BCM63268_GROUP(gpio7),
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+ BCM63268_GROUP(gpio8),
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+ BCM63268_GROUP(gpio9),
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+ BCM63268_GROUP(gpio10),
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+ BCM63268_GROUP(gpio11),
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+ BCM63268_GROUP(gpio12),
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+ BCM63268_GROUP(gpio13),
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+ BCM63268_GROUP(gpio14),
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+ BCM63268_GROUP(gpio15),
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+ BCM63268_GROUP(gpio16),
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+ BCM63268_GROUP(gpio17),
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+ BCM63268_GROUP(gpio18),
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+ BCM63268_GROUP(gpio19),
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+ BCM63268_GROUP(gpio20),
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+ BCM63268_GROUP(gpio21),
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+ BCM63268_GROUP(gpio22),
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+ BCM63268_GROUP(gpio23),
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+ BCM63268_GROUP(gpio24),
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+ BCM63268_GROUP(gpio25),
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+ BCM63268_GROUP(gpio26),
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+ BCM63268_GROUP(gpio27),
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+ BCM63268_GROUP(gpio28),
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+ BCM63268_GROUP(gpio29),
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+ BCM63268_GROUP(gpio30),
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+ BCM63268_GROUP(gpio31),
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+ BCM63268_GROUP(gpio32),
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+ BCM63268_GROUP(gpio33),
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+ BCM63268_GROUP(gpio34),
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+ BCM63268_GROUP(gpio35),
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+ BCM63268_GROUP(gpio36),
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+ BCM63268_GROUP(gpio37),
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+ BCM63268_GROUP(gpio38),
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+ BCM63268_GROUP(gpio39),
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+ BCM63268_GROUP(gpio40),
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+ BCM63268_GROUP(gpio41),
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+ BCM63268_GROUP(gpio42),
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+ BCM63268_GROUP(gpio43),
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+ BCM63268_GROUP(gpio44),
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+ BCM63268_GROUP(gpio45),
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+ BCM63268_GROUP(gpio46),
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+ BCM63268_GROUP(gpio47),
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+ BCM63268_GROUP(gpio48),
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+ BCM63268_GROUP(gpio49),
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+ BCM63268_GROUP(gpio50),
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+ BCM63268_GROUP(gpio51),
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+
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+ /* multi pin groups */
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+ BCM63268_GROUP(nand_grp),
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+ BCM63268_GROUP(dectpd_grp),
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+ BCM63268_GROUP(vdsl_phy0_grp),
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+ BCM63268_GROUP(vdsl_phy1_grp),
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+ BCM63268_GROUP(vdsl_phy2_grp),
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+ BCM63268_GROUP(vdsl_phy3_grp),
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+};
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+
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+static const char * const led_groups[] = {
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+ "gpio0",
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+ "gpio1",
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+ "gpio2",
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+ "gpio3",
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+ "gpio4",
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+ "gpio5",
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+ "gpio6",
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+ "gpio7",
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+ "gpio8",
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+ "gpio9",
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+ "gpio10",
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+ "gpio11",
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+ "gpio12",
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+ "gpio13",
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+ "gpio14",
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+ "gpio15",
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+ "gpio16",
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+ "gpio17",
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+ "gpio18",
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+ "gpio19",
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+ "gpio20",
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+ "gpio21",
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+ "gpio22",
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+ "gpio23",
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+};
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+
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+static const char * const serial_led_clk_groups[] = {
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+ "gpio0",
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+};
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+
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+static const char * const serial_led_data_groups[] = {
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+ "gpio1",
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+};
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+
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+static const char * const hsspi_cs4_groups[] = {
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+ "gpio16",
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+};
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+
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+static const char * const hsspi_cs5_groups[] = {
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+ "gpio17",
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+};
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+
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+static const char * const hsspi_cs6_groups[] = {
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+ "gpio8",
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+};
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+
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+static const char * const hsspi_cs7_groups[] = {
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+ "gpio9",
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+};
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+
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+static const char * const uart1_scts_groups[] = {
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+ "gpio10",
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+ "gpio24",
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+};
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+
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+static const char * const uart1_srts_groups[] = {
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+ "gpio11",
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+ "gpio25",
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+};
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+
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+static const char * const uart1_sdin_groups[] = {
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+ "gpio12",
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+ "gpio26",
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+};
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+
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+static const char * const uart1_sdout_groups[] = {
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+ "gpio13",
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+ "gpio27",
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+};
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+
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+static const char * const ntr_pulse_in_groups[] = {
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+ "gpio14",
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+ "gpio28",
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+};
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+
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+static const char * const dsl_ntr_pulse_out_groups[] = {
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+ "gpio15",
|
|
+ "gpio29",
|
|
+};
|
|
+
|
|
+static const char * const adsl_spi_miso_groups[] = {
|
|
+ "gpio18",
|
|
+};
|
|
+
|
|
+static const char * const adsl_spi_mosi_groups[] = {
|
|
+ "gpio19",
|
|
+};
|
|
+
|
|
+static const char * const vreg_clk_groups[] = {
|
|
+ "gpio22",
|
|
+};
|
|
+
|
|
+static const char * const pcie_clkreq_b_groups[] = {
|
|
+ "gpio23",
|
|
+};
|
|
+
|
|
+static const char * const switch_led_clk_groups[] = {
|
|
+ "gpio30",
|
|
+};
|
|
+
|
|
+static const char * const switch_led_data_groups[] = {
|
|
+ "gpio31",
|
|
+};
|
|
+
|
|
+static const char * const wifi_groups[] = {
|
|
+ "gpio32",
|
|
+ "gpio33",
|
|
+ "gpio34",
|
|
+ "gpio35",
|
|
+ "gpio36",
|
|
+ "gpio37",
|
|
+ "gpio38",
|
|
+ "gpio39",
|
|
+ "gpio40",
|
|
+ "gpio41",
|
|
+ "gpio42",
|
|
+ "gpio43",
|
|
+ "gpio44",
|
|
+ "gpio45",
|
|
+ "gpio46",
|
|
+ "gpio47",
|
|
+ "gpio48",
|
|
+ "gpio49",
|
|
+ "gpio50",
|
|
+ "gpio51",
|
|
+};
|
|
+
|
|
+static const char * const nand_groups[] = {
|
|
+ "nand_grp",
|
|
+};
|
|
+
|
|
+static const char * const dectpd_groups[] = {
|
|
+ "dectpd_grp",
|
|
+};
|
|
+
|
|
+static const char * const vdsl_phy_override_0_groups[] = {
|
|
+ "vdsl_phy_override_0_grp",
|
|
+};
|
|
+
|
|
+static const char * const vdsl_phy_override_1_groups[] = {
|
|
+ "vdsl_phy_override_1_grp",
|
|
+};
|
|
+
|
|
+static const char * const vdsl_phy_override_2_groups[] = {
|
|
+ "vdsl_phy_override_2_grp",
|
|
+};
|
|
+
|
|
+static const char * const vdsl_phy_override_3_groups[] = {
|
|
+ "vdsl_phy_override_3_grp",
|
|
+};
|
|
+
|
|
+#define BCM63268_LED_FUN(n) \
|
|
+ { \
|
|
+ .name = #n, \
|
|
+ .groups = n##_groups, \
|
|
+ .num_groups = ARRAY_SIZE(n##_groups), \
|
|
+ .reg = BCM63268_LEDCTRL, \
|
|
+ }
|
|
+
|
|
+#define BCM63268_MODE_FUN(n) \
|
|
+ { \
|
|
+ .name = #n, \
|
|
+ .groups = n##_groups, \
|
|
+ .num_groups = ARRAY_SIZE(n##_groups), \
|
|
+ .reg = BCM63268_MODE, \
|
|
+ }
|
|
+
|
|
+#define BCM63268_CTRL_FUN(n) \
|
|
+ { \
|
|
+ .name = #n, \
|
|
+ .groups = n##_groups, \
|
|
+ .num_groups = ARRAY_SIZE(n##_groups), \
|
|
+ .reg = BCM63268_CTRL, \
|
|
+ }
|
|
+
|
|
+#define BCM63268_BASEMODE_FUN(n, val) \
|
|
+ { \
|
|
+ .name = #n, \
|
|
+ .groups = n##_groups, \
|
|
+ .num_groups = ARRAY_SIZE(n##_groups), \
|
|
+ .reg = BCM63268_BASEMODE, \
|
|
+ .mask = val, \
|
|
+ }
|
|
+
|
|
+static const struct bcm63268_function bcm63268_funcs[] = {
|
|
+ BCM63268_LED_FUN(led),
|
|
+ BCM63268_MODE_FUN(serial_led_clk),
|
|
+ BCM63268_MODE_FUN(serial_led_data),
|
|
+ BCM63268_MODE_FUN(hsspi_cs6),
|
|
+ BCM63268_MODE_FUN(hsspi_cs7),
|
|
+ BCM63268_MODE_FUN(uart1_scts),
|
|
+ BCM63268_MODE_FUN(uart1_srts),
|
|
+ BCM63268_MODE_FUN(uart1_sdin),
|
|
+ BCM63268_MODE_FUN(uart1_sdout),
|
|
+ BCM63268_MODE_FUN(ntr_pulse_in),
|
|
+ BCM63268_MODE_FUN(dsl_ntr_pulse_out),
|
|
+ BCM63268_MODE_FUN(hsspi_cs4),
|
|
+ BCM63268_MODE_FUN(hsspi_cs5),
|
|
+ BCM63268_MODE_FUN(adsl_spi_miso),
|
|
+ BCM63268_MODE_FUN(adsl_spi_mosi),
|
|
+ BCM63268_MODE_FUN(vreg_clk),
|
|
+ BCM63268_MODE_FUN(pcie_clkreq_b),
|
|
+ BCM63268_MODE_FUN(switch_led_clk),
|
|
+ BCM63268_MODE_FUN(switch_led_data),
|
|
+ BCM63268_CTRL_FUN(wifi),
|
|
+ BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
|
|
+ BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
|
|
+ BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
|
|
+ BCM63268_BASEMODE_VDSL_PHY_0),
|
|
+ BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
|
|
+ BCM63268_BASEMODE_VDSL_PHY_1),
|
|
+ BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
|
|
+ BCM63268_BASEMODE_VDSL_PHY_2),
|
|
+ BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
|
|
+ BCM63268_BASEMODE_VDSL_PHY_3),
|
|
+};
|
|
+
|
|
+static inline unsigned int bcm63268_bank_pin(unsigned int pin)
|
|
+{
|
|
+ return pin % PINS_PER_BANK;
|
|
+}
|
|
+
|
|
+static inline unsigned int bcm63268_reg_off(unsigned int reg, unsigned int pin)
|
|
+{
|
|
+ return reg - (pin / PINS_PER_BANK) * BANK_SIZE;
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_direction_input(struct gpio_chip *chip,
|
|
+ unsigned int pin)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = gpiochip_get_data(chip);
|
|
+ unsigned int dirout = bcm63268_reg_off(BCM63268_DIROUT_REG, pin);
|
|
+ unsigned int bank_pin = bcm63268_bank_pin(pin);
|
|
+ int ret;
|
|
+
|
|
+ /*
|
|
+ * Check with the pinctrl driver whether this pin is usable as
|
|
+ * an input GPIO
|
|
+ */
|
|
+ ret = pinctrl_gpio_direction_input(chip->base + pin);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ regmap_update_bits(pc->regs, dirout, BIT(bank_pin), 0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_direction_output(struct gpio_chip *chip,
|
|
+ unsigned int pin, int value)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = gpiochip_get_data(chip);
|
|
+ unsigned int data = bcm63268_reg_off(BCM63268_DATA_REG, pin);
|
|
+ unsigned int dirout = bcm63268_reg_off(BCM63268_DIROUT_REG, pin);
|
|
+ unsigned int bank_pin = bcm63268_bank_pin(pin);
|
|
+ unsigned int val = value ? BIT(bank_pin) : 0;
|
|
+ int ret;
|
|
+
|
|
+ /*
|
|
+ * Check with the pinctrl driver whether this pin is usable as
|
|
+ * an output GPIO
|
|
+ */
|
|
+ ret = pinctrl_gpio_direction_output(chip->base + pin);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ regmap_update_bits(pc->regs, dirout, BIT(bank_pin), BIT(bank_pin));
|
|
+ regmap_update_bits(pc->regs, data, BIT(bank_pin), val);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_get(struct gpio_chip *chip, unsigned int pin)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = gpiochip_get_data(chip);
|
|
+ unsigned int data = bcm63268_reg_off(BCM63268_DATA_REG, pin);
|
|
+ unsigned int bank_pin = bcm63268_bank_pin(pin);
|
|
+ unsigned int val;
|
|
+
|
|
+ regmap_read(pc->regs, data, &val);
|
|
+
|
|
+ return !!(val & BIT(bank_pin));
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = gpiochip_get_data(chip);
|
|
+ unsigned int dirout = bcm63268_reg_off(BCM63268_DIROUT_REG, pin);
|
|
+ unsigned int bank_pin = bcm63268_bank_pin(pin);
|
|
+ unsigned int val;
|
|
+
|
|
+ regmap_read(pc->regs, dirout, &val);
|
|
+
|
|
+ if (val & BIT(bank_pin))
|
|
+ return GPIO_LINE_DIRECTION_OUT;
|
|
+
|
|
+ return GPIO_LINE_DIRECTION_IN;
|
|
+}
|
|
+
|
|
+static void bcm63268_gpio_set(struct gpio_chip *chip, unsigned int pin,
|
|
+ int value)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = gpiochip_get_data(chip);
|
|
+ unsigned int data = bcm63268_reg_off(BCM63268_DATA_REG, pin);
|
|
+ unsigned int bank_pin = bcm63268_bank_pin(pin);
|
|
+ unsigned int val = value ? BIT(bank_pin) : 0;
|
|
+
|
|
+ regmap_update_bits(pc->regs, data, BIT(bank_pin), val);
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ char irq_name[7];
|
|
+
|
|
+ sprintf(irq_name, "gpio%d", gpio);
|
|
+
|
|
+ return of_irq_get_byname(chip->of_node, irq_name);
|
|
+}
|
|
+
|
|
+static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
|
|
+{
|
|
+ return ARRAY_SIZE(bcm63268_groups);
|
|
+}
|
|
+
|
|
+static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
|
|
+ unsigned group)
|
|
+{
|
|
+ return bcm63268_groups[group].name;
|
|
+}
|
|
+
|
|
+static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|
+ unsigned group,
|
|
+ const unsigned **pins,
|
|
+ unsigned *num_pins)
|
|
+{
|
|
+ *pins = bcm63268_groups[group].pins;
|
|
+ *num_pins = bcm63268_groups[group].num_pins;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
|
|
+{
|
|
+ return ARRAY_SIZE(bcm63268_funcs);
|
|
+}
|
|
+
|
|
+static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
|
|
+ unsigned selector)
|
|
+{
|
|
+ return bcm63268_funcs[selector].name;
|
|
+}
|
|
+
|
|
+static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
|
|
+ unsigned selector,
|
|
+ const char * const **groups,
|
|
+ unsigned * const num_groups)
|
|
+{
|
|
+ *groups = bcm63268_funcs[selector].groups;
|
|
+ *num_groups = bcm63268_funcs[selector].num_groups;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void bcm63268_set_gpio(struct bcm63268_pinctrl *pc, unsigned pin)
|
|
+{
|
|
+ const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
|
|
+ unsigned int basemode = (unsigned long) desc->drv_data;
|
|
+ unsigned int mask = BIT(bcm63268_bank_pin(pin));
|
|
+
|
|
+ if (basemode)
|
|
+ regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
|
|
+ 0);
|
|
+
|
|
+ if (pin < PINS_PER_BANK) {
|
|
+ /* base mode: 0 => gpio, 1 => mux function */
|
|
+ regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
|
|
+
|
|
+ /* pins 0-23 might be muxed to led */
|
|
+ if (pin < BCM63268_NUM_LEDS)
|
|
+ regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
|
|
+ 0);
|
|
+ } else if (pin < BCM63268_NUM_GPIOS) {
|
|
+ /* ctrl reg: 0 => wifi function, 1 => gpio */
|
|
+ regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
|
|
+ }
|
|
+}
|
|
+
|
|
+static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
|
|
+ unsigned selector, unsigned group)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
|
|
+ const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
|
|
+ const struct bcm63268_function *f = &bcm63268_funcs[selector];
|
|
+ unsigned i;
|
|
+ unsigned int reg;
|
|
+ unsigned int val, mask;
|
|
+
|
|
+ for (i = 0; i < pg->num_pins; i++)
|
|
+ bcm63268_set_gpio(pc, pg->pins[i]);
|
|
+
|
|
+ switch (f->reg) {
|
|
+ case BCM63268_LEDCTRL:
|
|
+ reg = BCM63268_LED_REG;
|
|
+ mask = BIT(pg->pins[0]);
|
|
+ val = BIT(pg->pins[0]);
|
|
+ break;
|
|
+ case BCM63268_MODE:
|
|
+ reg = BCM63268_MODE_REG;
|
|
+ mask = BIT(pg->pins[0]);
|
|
+ val = BIT(pg->pins[0]);
|
|
+ break;
|
|
+ case BCM63268_CTRL:
|
|
+ reg = BCM63268_CTRL_REG;
|
|
+ mask = BIT(pg->pins[0]);
|
|
+ val = 0;
|
|
+ break;
|
|
+ case BCM63268_BASEMODE:
|
|
+ reg = BCM63268_BASEMODE_REG;
|
|
+ mask = f->mask;
|
|
+ val = f->mask;
|
|
+ break;
|
|
+ default:
|
|
+ WARN_ON(1);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ regmap_update_bits(pc->regs, reg, mask, val);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|
+ struct pinctrl_gpio_range *range,
|
|
+ unsigned offset)
|
|
+{
|
|
+ struct bcm63268_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
|
|
+
|
|
+ /* disable all functions using this pin */
|
|
+ bcm63268_set_gpio(pc, offset);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct pinctrl_ops bcm63268_pctl_ops = {
|
|
+ .get_groups_count = bcm63268_pinctrl_get_group_count,
|
|
+ .get_group_name = bcm63268_pinctrl_get_group_name,
|
|
+ .get_group_pins = bcm63268_pinctrl_get_group_pins,
|
|
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
|
+ .dt_free_map = pinctrl_utils_free_map,
|
|
+};
|
|
+
|
|
+static struct pinmux_ops bcm63268_pmx_ops = {
|
|
+ .get_functions_count = bcm63268_pinctrl_get_func_count,
|
|
+ .get_function_name = bcm63268_pinctrl_get_func_name,
|
|
+ .get_function_groups = bcm63268_pinctrl_get_groups,
|
|
+ .set_mux = bcm63268_pinctrl_set_mux,
|
|
+ .gpio_request_enable = bcm63268_gpio_request_enable,
|
|
+ .strict = true,
|
|
+};
|
|
+
|
|
+static int bcm63268_pinctrl_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct device_node *np = dev->of_node;
|
|
+ struct bcm63268_pinctrl *pc;
|
|
+ int err;
|
|
+
|
|
+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
|
|
+ if (!pc)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ platform_set_drvdata(pdev, pc);
|
|
+ pc->dev = dev;
|
|
+
|
|
+ pc->regs = syscon_node_to_regmap(dev->parent->of_node);
|
|
+ if (IS_ERR(pc->regs))
|
|
+ return PTR_ERR(pc->regs);
|
|
+
|
|
+ pc->gpio_chip.label = MODULE_NAME;
|
|
+ pc->gpio_chip.owner = THIS_MODULE;
|
|
+ pc->gpio_chip.request = gpiochip_generic_request;
|
|
+ pc->gpio_chip.free = gpiochip_generic_free;
|
|
+ pc->gpio_chip.direction_input = bcm63268_gpio_direction_input;
|
|
+ pc->gpio_chip.direction_output = bcm63268_gpio_direction_output;
|
|
+ pc->gpio_chip.get_direction = bcm63268_gpio_get_direction;
|
|
+ pc->gpio_chip.get = bcm63268_gpio_get;
|
|
+ pc->gpio_chip.set = bcm63268_gpio_set;
|
|
+ pc->gpio_chip.set_config = gpiochip_generic_config;
|
|
+ pc->gpio_chip.base = -1;
|
|
+ pc->gpio_chip.ngpio = BCM63268_NUM_GPIOS;
|
|
+ pc->gpio_chip.can_sleep = false;
|
|
+ pc->gpio_chip.parent = dev;
|
|
+ pc->gpio_chip.of_node = np;
|
|
+
|
|
+ if (of_get_property(np, "interrupt-names", NULL))
|
|
+ pc->gpio_chip.to_irq = bcm63268_gpio_to_irq;
|
|
+
|
|
+ err = gpiochip_add_data(&pc->gpio_chip, pc);
|
|
+ if (err) {
|
|
+ dev_err(dev, "could not add GPIO chip\n");
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ pc->pctl_desc.name = MODULE_NAME,
|
|
+ pc->pctl_desc.pins = bcm63268_pins,
|
|
+ pc->pctl_desc.npins = ARRAY_SIZE(bcm63268_pins),
|
|
+ pc->pctl_desc.pctlops = &bcm63268_pctl_ops,
|
|
+ pc->pctl_desc.pmxops = &bcm63268_pmx_ops,
|
|
+ pc->pctl_desc.owner = THIS_MODULE,
|
|
+
|
|
+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
|
|
+ if (IS_ERR(pc->pctl_dev)) {
|
|
+ gpiochip_remove(&pc->gpio_chip);
|
|
+ return PTR_ERR(pc->pctl_dev);
|
|
+ }
|
|
+
|
|
+ pc->gpio_range.name = MODULE_NAME;
|
|
+ pc->gpio_range.npins = BCM63268_NUM_GPIOS;
|
|
+ pc->gpio_range.base = pc->gpio_chip.base;
|
|
+ pc->gpio_range.gc = &pc->gpio_chip;
|
|
+ pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
|
|
+
|
|
+ dev_info(dev, "registered\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id bcm63268_pinctrl_match[] = {
|
|
+ { .compatible = "brcm,bcm63268-pinctrl", },
|
|
+ { },
|
|
+};
|
|
+
|
|
+static struct platform_driver bcm63268_pinctrl_driver = {
|
|
+ .probe = bcm63268_pinctrl_probe,
|
|
+ .driver = {
|
|
+ .name = MODULE_NAME,
|
|
+ .of_match_table = bcm63268_pinctrl_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+builtin_platform_driver(bcm63268_pinctrl_driver);
|