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182 lines
7.0 KiB
Diff
182 lines
7.0 KiB
Diff
From 1fa7016f17e440f19a7895b795384f105772dbfe Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Tue, 21 May 2019 13:36:52 +0100
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Subject: [PATCH 548/725] dwc_otg: Choose appropriate IRQ handover strategy
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2711 has no MPHI peripheral, but the ARM Control block can fake
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interrupts. Use the size of the DTB "mphi" reg block to determine
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which is required.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/usb/host/dwc_otg/dwc_otg_driver.c | 9 +++--
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 21 ++++++----
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 +
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drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 12 ++++--
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drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 41 +++++++++++++-------
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drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 3 ++
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6 files changed, 60 insertions(+), 28 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
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@@ -806,14 +806,15 @@ static int dwc_otg_driver_probe(
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if (!request_mem_region(_dev->resource[1].start,
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_dev->resource[1].end - _dev->resource[1].start + 1,
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"dwc_otg")) {
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- dev_dbg(&_dev->dev, "error reserving mapped memory\n");
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- retval = -EFAULT;
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- goto fail;
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- }
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+ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
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+ retval = -EFAULT;
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+ goto fail;
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+ }
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dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
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_dev->resource[1].end -
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_dev->resource[1].start + 1);
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+ dwc_otg_device->os_dep.use_swirq = (_dev->resource[1].end - _dev->resource[1].start) == 0x200;
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}
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#else
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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@@ -1347,8 +1347,12 @@ void notrace dwc_otg_fiq_fsm(struct fiq_
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/* We got an interrupt, didn't handle it. */
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if (kick_irq) {
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state->mphi_int_count++;
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- FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
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- FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
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+ if (state->mphi_regs.swirq_set) {
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+ FIQ_WRITE(state->mphi_regs.swirq_set, 1);
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+ } else {
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+ FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
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+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
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+ }
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}
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state->fiq_done++;
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@@ -1406,11 +1410,14 @@ void notrace dwc_otg_fiq_nop(struct fiq_
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state->mphi_int_count++;
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gintmsk.d32 &= state->gintmsk_saved.d32;
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FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
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- /* Force a clear before another dummy send */
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- FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
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- FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
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- FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
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-
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+ if (state->mphi_regs.swirq_set) {
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+ FIQ_WRITE(state->mphi_regs.swirq_set, 1);
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+ } else {
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+ /* Force a clear before another dummy send */
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+ FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
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+ FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
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+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
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+ }
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}
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state->fiq_done++;
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mb();
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
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@@ -118,6 +118,8 @@ typedef struct {
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volatile void* outdda;
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volatile void* outddb;
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volatile void* intstat;
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+ volatile void* swirq_set;
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+ volatile void* swirq_clr;
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} mphi_regs_t;
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enum fiq_debug_level {
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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@@ -220,16 +220,20 @@ exit_handler_routine:
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/* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
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if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
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+ if (dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr) {
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+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr, 1);
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+ } else {
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DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
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- if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
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- fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
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+ }
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+ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
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+ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
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DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
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while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
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;
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DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
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dwc_otg_hcd->fiq_state->mphi_int_count = 0;
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- }
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- int_done++;
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+ }
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+ int_done++;
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}
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haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
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/* Re-enable interrupts that the FIQ masked (first time round) */
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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@@ -474,22 +474,37 @@ static void hcd_init_fiq(void *cookie)
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set_fiq_regs(®s);
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#endif
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- //Set the mphi periph to the required registers
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- dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
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- dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
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- dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
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- dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
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- dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
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dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
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- DWC_WARN("MPHI regs_base at %px", dwc_otg_hcd->fiq_state->mphi_regs.base);
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- //Enable mphi peripheral
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- writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
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+ //Set the mphi periph to the required registers
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+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
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+ if (otg_dev->os_dep.use_swirq) {
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+ dwc_otg_hcd->fiq_state->mphi_regs.swirq_set =
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+ otg_dev->os_dep.mphi_base + 0x1f0;
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+ dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr =
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+ otg_dev->os_dep.mphi_base + 0x1f4;
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+ DWC_WARN("Fake MPHI regs_base at 0x%08x",
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+ (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
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+ } else {
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+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl =
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+ otg_dev->os_dep.mphi_base + 0x4c;
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+ dwc_otg_hcd->fiq_state->mphi_regs.outdda
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+ = otg_dev->os_dep.mphi_base + 0x28;
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+ dwc_otg_hcd->fiq_state->mphi_regs.outddb
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+ = otg_dev->os_dep.mphi_base + 0x2c;
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+ dwc_otg_hcd->fiq_state->mphi_regs.intstat
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+ = otg_dev->os_dep.mphi_base + 0x50;
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+ DWC_WARN("MPHI regs_base at %px",
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+ dwc_otg_hcd->fiq_state->mphi_regs.base);
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+
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+ //Enable mphi peripheral
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+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
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#ifdef DEBUG
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- if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
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- DWC_WARN("MPHI periph has been enabled");
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- else
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- DWC_WARN("MPHI periph has NOT been enabled");
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+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
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+ DWC_WARN("MPHI periph has been enabled");
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+ else
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+ DWC_WARN("MPHI periph has NOT been enabled");
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#endif
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+ }
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// Enable FIQ interrupt from USB peripheral
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#ifdef CONFIG_ARM64
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irq = otg_dev->os_dep.fiq_num;
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--- a/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
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@@ -102,6 +102,9 @@ typedef struct os_dependent {
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/** Base address for MPHI peripheral */
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void *mphi_base;
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+ /** mphi_base actually points to the SWIRQ block */
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+ bool use_swirq;
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+
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/** IRQ number (<0 if not valid) */
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int irq_num;
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