mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
796ad2f7ef
Hardware spec of DIR-842 C3: SoC: QCA9563 DRAM: 128MB DDR2 Flash: 16MB SPI-NOR Switch: QCA8337N WiFi 5.8GHz: QCA9888 WiFi 2.4Ghz: QCA9563 USB: circuit onboard, but components are not soldered Flash instructions: 1. Upgrade the factory.bin through the factory web interface or the u-boot failsafe interface. The firmware will boot up correctly for the first time. Do not power off the device after OpenWrt has booted. Otherwise the u-boot will enter failsafe mode as the checksum of the firmware has been changed. 2. Upgrade the sysupgrade.bin in OpenWrt. After upgrading completes the u-boot won't complain about the firmware checksum and it's OK to use now. 3. If you powered off the device before upgrading the sysupgrade.bin, just upgrade the factory.bin through the u-boot failsafe interface and then goto step 2. Signed-off-by: Perry Melange <isprotejesvalkata@gmail.com>
42 lines
753 B
Plaintext
42 lines
753 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
/dts-v1/;
|
|
|
|
#include "qca9563_dlink_dir-842-c.dtsi"
|
|
|
|
/ {
|
|
compatible = "dlink,dir-842-c3", "qca,qca9563";
|
|
model = "D-Link DIR-842 C3";
|
|
|
|
aliases {
|
|
led-boot = &power;
|
|
led-failsafe = &power;
|
|
led-running = &power;
|
|
led-upgrade = &power;
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
wps {
|
|
label = "dir-842-c3:green:wps";
|
|
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
power: power {
|
|
label = "dir-842-c3:green:power";
|
|
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
internet {
|
|
label = "dir-842-c3:green:internet";
|
|
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wlan {
|
|
label = "dir-842-c3:green:wlan";
|
|
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy0tpt";
|
|
};
|
|
};
|
|
};
|