mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 17:48:58 +00:00
20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
70 lines
2.0 KiB
Diff
70 lines
2.0 KiB
Diff
From ac0b202c0bae166810c63e2ac5067b6ea3f4af43 Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Mon, 17 Jan 2022 17:31:06 +0100
|
|
Subject: [PATCH] clk: bcm: rpi: Set a default minimum rate
|
|
|
|
The M2MC clock provides the state machine clock for both HDMI
|
|
controllers.
|
|
|
|
However, if no HDMI monitor is plugged in at boot, its clock rate will
|
|
be left at 0 by the firmware and will make any register access end up in
|
|
a CPU stall, even though the clock was enabled.
|
|
|
|
We had some code in the HDMI controller to deal with this before, but it
|
|
makes more sense to have it in the clock driver. Move it there.
|
|
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/clk/bcm/clk-raspberrypi.c | 26 ++++++++++++++++++++++++++
|
|
1 file changed, 26 insertions(+)
|
|
|
|
--- a/drivers/clk/bcm/clk-raspberrypi.c
|
|
+++ b/drivers/clk/bcm/clk-raspberrypi.c
|
|
@@ -78,6 +78,7 @@ struct raspberrypi_clk_data {
|
|
struct raspberrypi_clk_variant {
|
|
bool export;
|
|
char *clkdev;
|
|
+ unsigned long min_rate;
|
|
};
|
|
|
|
static struct raspberrypi_clk_variant
|
|
@@ -91,6 +92,18 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NU
|
|
},
|
|
[RPI_FIRMWARE_M2MC_CLK_ID] = {
|
|
.export = true,
|
|
+
|
|
+ /*
|
|
+ * If we boot without any cable connected to any of the
|
|
+ * HDMI connector, the firmware will skip the HSM
|
|
+ * initialization and leave it with a rate of 0,
|
|
+ * resulting in a bus lockup when we're accessing the
|
|
+ * registers even if it's enabled.
|
|
+ *
|
|
+ * Let's put a sensible default so that we don't end up
|
|
+ * in this situation.
|
|
+ */
|
|
+ .min_rate = 120000000,
|
|
},
|
|
[RPI_FIRMWARE_V3D_CLK_ID] = {
|
|
.export = true,
|
|
@@ -278,6 +291,19 @@ static struct clk_hw *raspberrypi_clk_re
|
|
}
|
|
}
|
|
|
|
+ if (variant->min_rate) {
|
|
+ unsigned long rate;
|
|
+
|
|
+ clk_hw_set_rate_range(&data->hw, variant->min_rate, max_rate);
|
|
+
|
|
+ rate = raspberrypi_fw_get_rate(&data->hw, 0);
|
|
+ if (rate < variant->min_rate) {
|
|
+ ret = raspberrypi_fw_set_rate(&data->hw, variant->min_rate, 0);
|
|
+ if (ret)
|
|
+ return ERR_PTR(ret);
|
|
+ }
|
|
+ }
|
|
+
|
|
return &data->hw;
|
|
}
|
|
|