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Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
56 lines
1.9 KiB
Diff
56 lines
1.9 KiB
Diff
From acc8ac41d15594d4f735531c89bbeb03d85c344d Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 8 Oct 2020 16:06:08 +0200
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Subject: [PATCH] drm/vc4: hdmi: Properly compute the BVB clock rate
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The BVB clock rate computation doesn't take into account a mode clock of
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594MHz that we're going to need to support 4k60.
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Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
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Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++--------
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1 file changed, 9 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -93,7 +93,6 @@
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#define HSM_MIN_CLOCK_FREQ 120000000
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#define CEC_CLOCK_FREQ 40000
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-#define VC4_HSM_MID_CLOCK 149985000
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#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
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@@ -816,7 +815,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
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conn_state_to_vc4_hdmi_conn_state(conn_state);
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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- unsigned long pixel_rate, hsm_rate;
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+ unsigned long bvb_rate, pixel_rate, hsm_rate;
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int ret;
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ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
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@@ -865,12 +864,14 @@ static void vc4_hdmi_encoder_pre_crtc_co
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vc4_hdmi_cec_update_clk_div(vc4_hdmi);
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- /*
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- * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
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- * at 300MHz.
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- */
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- vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
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- (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
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+ if (pixel_rate > 297000000)
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+ bvb_rate = 300000000;
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+ else if (pixel_rate > 148500000)
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+ bvb_rate = 150000000;
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+ else
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+ bvb_rate = 75000000;
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+
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+ vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate);
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if (IS_ERR(vc4_hdmi->bvb_req)) {
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DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
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clk_request_done(vc4_hdmi->hsm_req);
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