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Hardware -------- RockChip RK3588 ARM64 (8 cores) 4/8/16/32GB LPDDR4X RAM 2500 Base-T RGB LED eMMC Connector SPI-NOR 16MB Micro-SD Slot 2x USB 2.0 Port 2x USB 3.0 Port Headphone Jack M.2 E-Key M.2 M-Key USB PD 5/9/12/15/20V Power Install -------- Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
81 lines
2.1 KiB
Diff
81 lines
2.1 KiB
Diff
From da447ec387800bdf2df1fb1d8c1522991d025952 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Mon, 18 Sep 2023 16:14:51 +0200
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Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b
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Enable PCIe2_0 controller and its voltage supply, which is routed
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to the M.2 E-Key on the upper side of the Radxa Rock 5B.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
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1 file changed, 35 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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@@ -43,6 +43,21 @@
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#cooling-cells = <2>;
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};
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+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
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+ regulator-name = "vcc3v3_pcie2x1l0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <50000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie2x1l2";
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@@ -103,6 +118,10 @@
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status = "okay";
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};
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+&combphy1_ps {
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+ status = "okay";
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+};
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+
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&cpu_b0 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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@@ -229,6 +248,14 @@
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};
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};
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+&pcie2x1l0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_0_rst>;
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+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
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+ status = "okay";
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+};
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+
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&pcie2x1l2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_2_rst>;
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@@ -263,6 +290,14 @@
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};
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pcie2 {
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+ pcie2_0_rst: pcie2-0-rst {
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+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
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+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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pcie2_2_rst: pcie2-2-rst {
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rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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