mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
703515f889
Includes the following changes:9edff13abdmac80211: disable potentially harmful PS software retry for A-MPDU sessions75216a76b0mac80211: backport upstream fix for CSA in IBSS mode368cc8ef47mac80211: update brcmfmac backporting brcmf_err cleanups66a63d25c4mac80211: fix build on linux 3.189eacb9d7fcrt2x00: mt7620: lots of improvementsfd94fa61a7mac80211: brcmfmac: update Raspberry Pi patches for linux 4.9649e766a64mac80211: update to wireless-testing 2017-01-3147540afa5dath9k: add a warning to the tx99 config optionb367eef21dmac80211: rt2x00: add support for external LNA on MT76209200e168f2mac80211: move (& update) upstream accepted brcmfmac patches Signed-off-by: Felix Fietkau <nbd@nbd.name>
187 lines
5.9 KiB
Diff
187 lines
5.9 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/hw.h
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+++ b/drivers/net/wireless/ath/ath9k/hw.h
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@@ -721,6 +721,7 @@ struct ath_spec_scan {
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* @config_pci_powersave:
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* @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
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*
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+ * @get_adc_entropy: get entropy from the raw ADC I/Q output
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* @spectral_scan_config: set parameters for spectral scan and enable/disable it
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* @spectral_scan_trigger: trigger a spectral scan run
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* @spectral_scan_wait: wait for a spectral scan run to finish
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@@ -743,6 +744,7 @@ struct ath_hw_ops {
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struct ath_hw_antcomb_conf *antconf);
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void (*antdiv_comb_conf_set)(struct ath_hw *ah,
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struct ath_hw_antcomb_conf *antconf);
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+ void (*get_adc_entropy)(struct ath_hw *ah, u8 *buf, size_t len);
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void (*spectral_scan_config)(struct ath_hw *ah,
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struct ath_spec_scan *param);
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void (*spectral_scan_trigger)(struct ath_hw *ah);
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@@ -1947,6 +1947,26 @@ void ar9003_hw_init_rate_txpower(struct
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}
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}
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+static void ar9003_hw_get_adc_entropy(struct ath_hw *ah, u8 *buf, size_t len)
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+{
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+ int i, j;
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+
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+ REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1);
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+ REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5);
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+ REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_RX_OBS_SEL, 0);
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+
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+ memset(buf, 0, len);
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+ for (i = 0; i < len; i++) {
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+ for (j = 0; j < 4; j++) {
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+ u32 regval = REG_READ(ah, AR_PHY_TST_ADC);
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+
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+ buf[i] <<= 2;
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+ buf[i] |= (regval & 1) | ((regval & BIT(10)) >> 9);
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+ udelay(1);
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+ }
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+ }
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+}
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+
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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@@ -1983,6 +2003,7 @@ void ar9003_hw_attach_phy_ops(struct ath
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priv_ops->set_radar_params = ar9003_hw_set_radar_params;
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priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
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+ ops->get_adc_entropy = ar9003_hw_get_adc_entropy;
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ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
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ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
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ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
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--- a/drivers/net/wireless/ath/ath9k/init.c
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+++ b/drivers/net/wireless/ath/ath9k/init.c
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@@ -765,7 +765,8 @@ static void ath9k_init_txpower_limits(st
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if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
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ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
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- ah->curchan = curchan;
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+ if (curchan)
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+ ah->curchan = curchan;
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}
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static const struct ieee80211_iface_limit if_limits[] = {
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@@ -958,6 +959,18 @@ static void ath9k_set_hw_capab(struct at
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SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
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}
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+static void ath_get_initial_entropy(struct ath_softc *sc)
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+{
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+ struct ath_hw *ah = sc->sc_ah;
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+ char buf[256];
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+
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+ /* reuse last channel initialized by the tx power test */
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+ ath9k_hw_reset(ah, ah->curchan, NULL, false);
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+
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+ ath9k_hw_get_adc_entropy(ah, buf, sizeof(buf));
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+ add_device_randomness(buf, sizeof(buf));
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+}
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+
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int ath9k_init_device(u16 devid, struct ath_softc *sc,
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const struct ath_bus_ops *bus_ops)
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{
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@@ -1003,6 +1016,8 @@ int ath9k_init_device(u16 devid, struct
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ARRAY_SIZE(ath9k_tpt_blink));
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#endif
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+ ath_get_initial_entropy(sc);
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+
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/* Register with mac80211 */
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error = ieee80211_register_hw(hw);
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if (error)
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--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
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+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
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@@ -100,6 +100,12 @@ static inline void ath9k_hw_tx99_set_txp
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ath9k_hw_ops(ah)->tx99_set_txpower(ah, power);
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}
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+static inline void ath9k_hw_get_adc_entropy(struct ath_hw *ah,
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+ u8 *buf, size_t len)
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+{
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+ ath9k_hw_ops(ah)->get_adc_entropy(ah, buf, len);
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+}
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+
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#ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
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static inline void ath9k_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
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--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
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@@ -1322,9 +1322,30 @@ void ar5008_hw_init_rate_txpower(struct
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}
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}
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+static void ar5008_hw_get_adc_entropy(struct ath_hw *ah, u8 *buf, size_t len)
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+{
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+ int i, j;
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+
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+ REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1);
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+ REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5);
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+ REG_RMW_FIELD(ah, AR_PHY_TEST2, AR_PHY_TEST2_RX_OBS_SEL, 0);
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+
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+ memset(buf, 0, len);
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+ for (i = 0; i < len; i++) {
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+ for (j = 0; j < 4; j++) {
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+ u32 regval = REG_READ(ah, AR_PHY_TST_ADC);
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+
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+ buf[i] <<= 2;
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+ buf[i] |= (regval & 1) | ((regval & BIT(9)) >> 8);
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+ udelay(1);
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+ }
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+ }
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+}
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+
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int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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+ struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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static const u32 ar5416_cca_regs[6] = {
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AR_PHY_CCA,
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AR_PHY_CH1_CCA,
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@@ -1339,6 +1360,8 @@ int ar5008_hw_attach_phy_ops(struct ath_
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if (ret)
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return ret;
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+ ops->get_adc_entropy = ar5008_hw_get_adc_entropy;
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+
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priv_ops->rf_set_freq = ar5008_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
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--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
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+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
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@@ -20,6 +20,12 @@
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#define PHY_AGC_CLR 0x10000000
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#define RFSILENT_BB 0x00002000
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+#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
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+#define AR_PHY_TEST_BBB_OBS_SEL_S 19
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+
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+#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
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+#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
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+
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#define AR_PHY_TURBO 0x9804
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#define AR_PHY_FC_TURBO_MODE 0x00000001
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#define AR_PHY_FC_TURBO_SHORT 0x00000002
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@@ -36,6 +42,9 @@
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#define AR_PHY_TEST2 0x9808
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+#define AR_PHY_TEST2_RX_OBS_SEL 0x3C00
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+#define AR_PHY_TEST2_RX_OBS_SEL_S 10
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+
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#define AR_PHY_TIMING2 0x9810
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#define AR_PHY_TIMING3 0x9814
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#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
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@@ -393,6 +402,8 @@
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#define AR_PHY_RFBUS_GRANT 0x9C20
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#define AR_PHY_RFBUS_GRANT_EN 0x00000001
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+#define AR_PHY_TST_ADC 0x9C24
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+
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#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
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#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
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