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124 lines
3.5 KiB
Diff
124 lines
3.5 KiB
Diff
From e84732bd6022dd12839dd34d508eb27428367c24 Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Wed, 20 Dec 2017 15:57:30 +0800
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Subject: [PATCH 219/224] arm64: dts: mt7622: add PCIe device nodes
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This patch adds PCIe support fot MT7622.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 10 ++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 74 ++++++++++++++++++++++++++++
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2 files changed, 84 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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index e2bd93e1b49b..72ef4434bcef 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -54,6 +54,16 @@
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};
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};
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie0_pins>;
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+ status = "okay";
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+
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+ pcie@0,0 {
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+ status = "okay";
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+ };
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+};
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+
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&pio {
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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index 95f947eb824c..cc026ebda2f4 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -542,6 +542,80 @@
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#reset-cells = <1>;
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};
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+ pcie: pcie@1a140000 {
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+ compatible = "mediatek,mt7622-pcie";
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+ device_type = "pci";
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+ reg = <0 0x1a140000 0 0x1000>,
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+ <0 0x1a143000 0 0x1000>,
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+ <0 0x1a145000 0 0x1000>;
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+ reg-names = "subsys", "port0", "port1";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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+ <&pciesys CLK_PCIE_P1_MAC_EN>,
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+ <&pciesys CLK_PCIE_P0_AHB_EN>,
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+ <&pciesys CLK_PCIE_P0_AHB_EN>,
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+ <&pciesys CLK_PCIE_P0_AUX_EN>,
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+ <&pciesys CLK_PCIE_P1_AUX_EN>,
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+ <&pciesys CLK_PCIE_P0_AXI_EN>,
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+ <&pciesys CLK_PCIE_P1_AXI_EN>,
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+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
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+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
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+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
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+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
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+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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+
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+ pcie0: pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ num-lanes = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ };
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+ };
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+
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+ pcie1: pcie@1,0 {
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+ reg = <0x0800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ num-lanes = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ };
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+ };
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+ };
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+
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7622-ethsys",
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"syscon";
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--
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2.11.0
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