mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
112 lines
3.2 KiB
Diff
112 lines
3.2 KiB
Diff
--- /dev/null
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+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
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@@ -0,0 +1,37 @@
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+/*
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+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
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+ * Copyright (C) 2003, 2004 Ralf Baechle
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
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+#define __ASM_MACH_ATH79_MANGLE_PORT_H
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+
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+#ifdef CONFIG_PCI
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+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
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+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
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+#else
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+#define ath79_pci_swizzle_b(port) (port)
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+#define ath79_pci_swizzle_w(port) (port)
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+#endif
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+
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+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
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+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
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+#define __swizzle_addr_l(port) (port)
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+#define __swizzle_addr_q(port) (port)
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+
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+# define ioswabb(a, x) (x)
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+# define __mem_ioswabb(a, x) (x)
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+# define ioswabw(a, x) (x)
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+# define __mem_ioswabw(a, x) cpu_to_le16(x)
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+# define ioswabl(a, x) (x)
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+# define __mem_ioswabl(a, x) cpu_to_le32(x)
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+# define ioswabq(a, x) (x)
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+# define __mem_ioswabq(a, x) cpu_to_le64(x)
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+
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+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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@@ -13,6 +13,7 @@
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*/
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#include <linux/init.h>
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+#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/resource.h>
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#include <linux/platform_device.h>
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@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
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static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
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static unsigned ath79_pci_nr_irqs __initdata;
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+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
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+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
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+
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static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
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{
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.slot = 17,
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@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
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return pdev;
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}
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+static inline bool ar71xx_is_pci_addr(unsigned long port)
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+{
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+ unsigned long phys = CPHYSADDR(port);
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+
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+ return (phys >= AR71XX_PCI_MEM_BASE &&
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+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
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+}
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+
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+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
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+{
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+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
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+}
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+
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+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
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+{
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+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
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+}
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+
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+unsigned long ath79_pci_swizzle_b(unsigned long port)
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+{
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+ if (__ath79_pci_swizzle_b)
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+ return __ath79_pci_swizzle_b(port);
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+
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+ return port;
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+}
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+EXPORT_SYMBOL(ath79_pci_swizzle_b);
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+
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+unsigned long ath79_pci_swizzle_w(unsigned long port)
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+{
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+ if (__ath79_pci_swizzle_w)
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+ return __ath79_pci_swizzle_w(port);
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+
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+ return port;
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+}
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+EXPORT_SYMBOL(ath79_pci_swizzle_w);
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+
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int __init ath79_register_pci(void)
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{
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struct platform_device *pdev = NULL;
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if (soc_is_ar71xx()) {
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pdev = ath79_register_pci_ar71xx();
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+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
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+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
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} else if (soc_is_ar724x()) {
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pdev = ath79_register_pci_ar724x(-1,
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AR724X_PCI_CFG_BASE,
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