mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
d2a2eb7e48
This driver has been cherry-picked and backported from the following LKML thread: *https://lkml.org/lkml/2015/5/26/744 It also updates the DT accordingly. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45831
53 lines
1.6 KiB
Diff
53 lines
1.6 KiB
Diff
From 0f9605d9409b77a89daef91cc68239fc2ff50457 Mon Sep 17 00:00:00 2001
|
|
From: Mathieu Olivari <mathieu@codeaurora.org>
|
|
Date: Fri, 8 May 2015 16:51:25 -0700
|
|
Subject: [PATCH 5/8] net: stmmac: ipq806x: document device tree bindings
|
|
|
|
Add the device tree bindings documentation for the QCA IPQ806x
|
|
variant of the Synopsys DesignWare MAC.
|
|
|
|
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|
---
|
|
.../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++
|
|
1 file changed, 35 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
|
|
@@ -0,0 +1,35 @@
|
|
+* IPQ806x DWMAC Ethernet controller
|
|
+
|
|
+The device inherits all the properties of the dwmac/stmmac devices
|
|
+described in the file net/stmmac.txt with the following changes.
|
|
+
|
|
+Required properties:
|
|
+
|
|
+- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
|
|
+ and any applicable more detailed version number
|
|
+ described in net/stmmac.txt
|
|
+
|
|
+- qcom,nss-common: should contain a phandle to a syscon device mapping the
|
|
+ nss-common registers.
|
|
+
|
|
+- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
|
|
+ qsgmii-csr registers.
|
|
+
|
|
+Example:
|
|
+
|
|
+ gmac: ethernet@37000000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac";
|
|
+ reg = <0x37000000 0x200000>;
|
|
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE1_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+ };
|