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Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.44 Removed upstreamed: rockchip/patches-6.6/044-v6.11-arm64-dts-rockchip-Add-sdmmc-related-properties-on-r.patch[1] rockchip/patches-6.6/045-v6.11-arm64-dts-rockchip-Add-pinctrl-for-UART0-to-rk3308-r.patch[2] rockchip/patches-6.6/046-v6.11-arm64-dts-rockchip-Add-mdio-and-ethernet-phy-nodes-t.patch[3] rockchip/patches-6.6/048-v6.11-arm64-dts-rockchip-Update-WIFi-BT-related-nodes-on-r.patch[4] rockchip/patches-6.6/310-PCI-dw-rockchip-Fix-initial-PERST-GPIO-value.patch[5] Manually rebased: bcm27xx/patches-6.6/950-0526-mfd-Add-rp1-driver.patch ramips/patches-6.6/810-uvc-add-iPassion-iP2970-support.patch All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.44&id=96155dc8c99e76a0e58932ca5f88148a37af3617 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.44&id=30ee9e5ecc5fd6854a1690ab11e6e6b4851ac9ab 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.44&id=0c4c1b7daf23bccf0da5b65b3cd5b32bfa5a5af4 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.44&id=a86a5685675834732789df202e73153db59d8dcc 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.44&id=a30211c6704899de0616ac0f97601122d899c86d Build system: x86/64 Build-tested: x86/64/AMD Cezanne Run-tested: x86/64/AMD Cezanne Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16061 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
93 lines
3.3 KiB
Diff
93 lines
3.3 KiB
Diff
From e3ab3267a0bbedc37725bb845a332ec33b247263 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 27 Feb 2024 18:54:22 +0100
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Subject: [PATCH 2/2] net: dsa: mv88e6xxx: add Amethyst specific SMI GPIO
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function
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The existing mv88e6390_g2_scratch_gpio_set_smi() cannot be used on the
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88E6393X as it requires certain P0_MODE, it also checks the CPU mode
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as it impacts the bit setting value.
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This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
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the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
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pin value but it can be changed without restrictions so that GPIO pins
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9 and 10 are used as SMI pins.
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So, introduce Amethyst specific function and call that if the Amethyst
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family wants to setup the external PHY.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/mv88e6xxx/chip.c | 5 +++-
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drivers/net/dsa/mv88e6xxx/global2.h | 2 ++
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drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++
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3 files changed, 37 insertions(+), 1 deletion(-)
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--- a/drivers/net/dsa/mv88e6xxx/chip.c
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+++ b/drivers/net/dsa/mv88e6xxx/chip.c
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@@ -3669,7 +3669,10 @@ static int mv88e6xxx_mdio_register(struc
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if (external) {
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mv88e6xxx_reg_lock(chip);
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- err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
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+ if (chip->info->family == MV88E6XXX_FAMILY_6393)
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+ err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
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+ else
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+ err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
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mv88e6xxx_reg_unlock(chip);
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if (err)
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--- a/drivers/net/dsa/mv88e6xxx/global2.h
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+++ b/drivers/net/dsa/mv88e6xxx/global2.h
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@@ -380,6 +380,8 @@ extern const struct mv88e6xxx_gpio_ops m
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int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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bool external);
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+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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+ bool external);
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int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
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int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
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int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
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--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c
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+++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
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@@ -291,6 +291,37 @@ int mv88e6390_g2_scratch_gpio_set_smi(st
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}
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/**
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+ * mv88e6393x_g2_scratch_gpio_set_smi - set gpio muxing for external smi
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+ * @chip: chip private data
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+ * @external: set mux for external smi, or free for gpio usage
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+ *
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+ * MV88E6191X/6193X/6393X GPIO pins 9 and 10 can be configured as an
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+ * external SMI interface or as regular GPIO-s.
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+ *
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+ * They however have a different register layout then the existing
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+ * function.
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+ */
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+
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+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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+ bool external)
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+{
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+ int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
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+ int err;
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+ u8 val;
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+
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+ err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
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+ if (err)
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+ return err;
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+
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+ if (external)
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+ val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
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+ else
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+ val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
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+
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+ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
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+}
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+
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+/**
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* mv88e6352_g2_scratch_port_has_serdes - indicate if a port can have a serdes
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* @chip: chip private data
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* @port: port number to check for serdes
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