mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
51db334005
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.54 Removed upstreamed: generic/backport-6.6/780-24-v6.12-r8169-disable-ALDPS-per-default-for-RTL8125.patch[1] generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch[2] Manually rebased: bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch bmips/patches-6.6/200-mips-bmips-automatically-detect-CPU-frequency.patch All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.54&id=50d062b6cc90c45a0de54e9bd9903c82777d66bf 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.54&id=103c0431c7fb4790affea121126840dbfb146341 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16602 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
106 lines
3.4 KiB
Diff
106 lines
3.4 KiB
Diff
From f61d5d294f12df46380ef1af5f55abe8e8f45500 Mon Sep 17 00:00:00 2001
|
|
From: Dom Cobley <popcornmix@gmail.com>
|
|
Date: Tue, 24 Oct 2023 16:20:42 +0100
|
|
Subject: [PATCH 0713/1085] drm/vc4: crtc: Support odd horizontal timings on
|
|
BCM2712
|
|
|
|
BCM2711 runs pixelvalve at two pixels per clock cycle which results
|
|
in an unfortunate limitation that odd horizontal timings are not
|
|
possible. This is apparent on the standard DMT mode of 1366x768@60
|
|
which cannot be driven with correct timing.
|
|
|
|
BCM2712 defaults to the same behaviour, but has a mode to support
|
|
odd timings. While internally it still runs at two pixels per clock,
|
|
setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally
|
|
to behave as it is one pixel per clock.
|
|
|
|
Switching to this mode fixes 1366x768@60 mode, and other custom
|
|
resultions with odd horizontal timings.
|
|
|
|
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_crtc.c | 12 ++++--------
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
|
|
drivers/gpu/drm/vc4/vc4_regs.h | 1 +
|
|
3 files changed, 7 insertions(+), 10 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
|
|
@@ -399,12 +399,6 @@ static void vc4_crtc_config_pv(struct dr
|
|
|
|
vc4_crtc_pixelvalve_reset(crtc);
|
|
|
|
- /*
|
|
- * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
|
|
- * bit that, when set, will allow to specify the timings in
|
|
- * pixels instead of cycles, thus allowing to specify odd
|
|
- * timings.
|
|
- */
|
|
CRTC_WRITE(PV_HORZA,
|
|
VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
|
|
PV_HORZA_HBP) |
|
|
@@ -449,6 +443,7 @@ static void vc4_crtc_config_pv(struct dr
|
|
*/
|
|
CRTC_WRITE(PV_V_CONTROL,
|
|
PV_VCONTROL_CONTINUOUS |
|
|
+ (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
|
|
(is_dsi ? PV_VCONTROL_DSI : 0) |
|
|
PV_VCONTROL_INTERLACE |
|
|
(odd_field_first
|
|
@@ -460,6 +455,7 @@ static void vc4_crtc_config_pv(struct dr
|
|
} else {
|
|
CRTC_WRITE(PV_V_CONTROL,
|
|
PV_VCONTROL_CONTINUOUS |
|
|
+ (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
|
|
(is_dsi ? PV_VCONTROL_DSI : 0));
|
|
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
|
|
}
|
|
@@ -1332,7 +1328,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
|
|
.hvs_output = 0,
|
|
},
|
|
.fifo_depth = 64,
|
|
- .pixels_per_clock = 2,
|
|
+ .pixels_per_clock = 1,
|
|
.encoder_types = {
|
|
[0] = VC4_ENCODER_TYPE_HDMI0,
|
|
},
|
|
@@ -1345,7 +1341,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
|
|
.hvs_output = 1,
|
|
},
|
|
.fifo_depth = 64,
|
|
- .pixels_per_clock = 2,
|
|
+ .pixels_per_clock = 1,
|
|
.encoder_types = {
|
|
[0] = VC4_ENCODER_TYPE_HDMI1,
|
|
},
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -3918,7 +3918,7 @@ static const struct vc4_hdmi_variant bcm
|
|
PHY_LANE_2,
|
|
PHY_LANE_CK,
|
|
},
|
|
- .unsupported_odd_h_timings = true,
|
|
+ .unsupported_odd_h_timings = false,
|
|
.external_irq_controller = true,
|
|
|
|
.init_resources = vc5_hdmi_init_resources,
|
|
@@ -3945,7 +3945,7 @@ static const struct vc4_hdmi_variant bcm
|
|
PHY_LANE_2,
|
|
PHY_LANE_CK,
|
|
},
|
|
- .unsupported_odd_h_timings = true,
|
|
+ .unsupported_odd_h_timings = false,
|
|
.external_irq_controller = true,
|
|
|
|
.init_resources = vc5_hdmi_init_resources,
|
|
--- a/drivers/gpu/drm/vc4/vc4_regs.h
|
|
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
|
|
@@ -155,6 +155,7 @@
|
|
# define PV_CONTROL_EN BIT(0)
|
|
|
|
#define PV_V_CONTROL 0x04
|
|
+# define PV_VCONTROL_ODD_TIMING BIT(29)
|
|
# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
|
|
# define PV_VCONTROL_ODD_DELAY_SHIFT 6
|
|
# define PV_VCONTROL_ODD_FIRST BIT(5)
|