openwrt/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts
Christian Lamparter b2aca5a263 ath79: fix various dts warnings
ar9344_openmesh_mr600-v1.dts:40.10-44.5: Warning (gpios_property):
/leds-ath9k/wifi2g: Missing property '#gpio-cells' in node
/ahb/pcie-controller@180c0000/wifi@0,0 or bad phandle
=> added gpio-controller + #gpio-cells

qca955x_zyxel_nbg6x16.dtsi:121.3-13: Warning (reg_format):
/ahb/usb@1b000000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
../dts/qca955x_zyxel_nbg6x16.dtsi:131.3-13: Warning (reg_format):
/ahb/usb@1b400000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
qca955x_zyxel_nbg6x16.dtsi:120.20-123.4: Warning (avoid_default_addr_size):
/ahb/usb@1b000000/port@1: Relying on default #address-cells value
=> ath79's usb-nodes are missing the address- and size-cells properties.
These are needed for usb led trigger support.

ar7242_ubnt_sw.dtsi:54.4-14: Warning (reg_format): /gpio_spi/gpio_spi@0:reg:
property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
=> the #address-cells and #size-cells had to be nudged.

qca9531_dlink_dch-g020-a1.dts:19.6-39.4: Warning (i2c_bus_bridge):
/i2c: incorrect #size-cells for I2C bus
=> #size-cells = <0>;

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2021-12-11 00:50:02 +01:00

202 lines
3.6 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar7242_ubnt_sw.dtsi"
/ {
compatible = "ubnt,edgeswitch-8xp", "qca,ar7242";
model = "Ubiquiti EdgeSwitch 8XP";
gpio-export {
compatible = "gpio-export";
poe_24v_port1 {
gpio-export,name = "ubnt:24v-poe:port1";
gpio-export,output = <0>;
gpios = <&gpio_hc595 1 GPIO_ACTIVE_HIGH>;
};
poe_48v_port1 {
gpio-export,name = "ubnt:48v-poe:port1";
gpio-export,output = <0>;
gpios = <&gpio_hc595 0 GPIO_ACTIVE_HIGH>;
};
poe_24v_port2 {
gpio-export,name = "ubnt:24v-poe:port2";
gpio-export,output = <0>;
gpios = <&gpio_hc595 3 GPIO_ACTIVE_HIGH>;
};
poe_48v_port2 {
gpio-export,name = "ubnt:48v-poe:port2";
gpio-export,output = <0>;
gpios = <&gpio_hc595 2 GPIO_ACTIVE_HIGH>;
};
poe_24v_port3 {
gpio-export,name = "ubnt:24v-poe:port3";
gpio-export,output = <0>;
gpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>;
};
poe_48v_port3 {
gpio-export,name = "ubnt:48v-poe:port3";
gpio-export,output = <0>;
gpios = <&gpio_hc595 4 GPIO_ACTIVE_HIGH>;
};
poe_24v_port4 {
gpio-export,name = "ubnt:24v-poe:port4";
gpio-export,output = <0>;
gpios = <&gpio_hc595 7 GPIO_ACTIVE_HIGH>;
};
poe_48v_port4 {
gpio-export,name = "ubnt:48v-poe:port4";
gpio-export,output = <0>;
gpios = <&gpio_hc595 6 GPIO_ACTIVE_HIGH>;
};
poe_24v_port5 {
gpio-export,name = "ubnt:24v-poe:port5";
gpio-export,output = <0>;
gpios = <&gpio_hc595 9 GPIO_ACTIVE_HIGH>;
};
poe_48v_port5 {
gpio-export,name = "ubnt:48v-poe:port5";
gpio-export,output = <0>;
gpios = <&gpio_hc595 8 GPIO_ACTIVE_HIGH>;
};
poe_24v_port6 {
gpio-export,name = "ubnt:24v-poe:port6";
gpio-export,output = <0>;
gpios = <&gpio_hc595 11 GPIO_ACTIVE_HIGH>;
};
poe_48v_port6 {
gpio-export,name = "ubnt:48v-poe:port6";
gpio-export,output = <0>;
gpios = <&gpio_hc595 10 GPIO_ACTIVE_HIGH>;
};
poe_24v_port7 {
gpio-export,name = "ubnt:24v-poe:port7";
gpio-export,output = <0>;
gpios = <&gpio_hc595 13 GPIO_ACTIVE_HIGH>;
};
poe_48v_port7 {
gpio-export,name = "ubnt:48v-poe:port7";
gpio-export,output = <0>;
gpios = <&gpio_hc595 12 GPIO_ACTIVE_HIGH>;
};
poe_24v_port8 {
gpio-export,name = "ubnt:24v-poe:port8";
gpio-export,output = <0>;
gpios = <&gpio_hc595 15 GPIO_ACTIVE_HIGH>;
};
poe_48v_port8 {
gpio-export,name = "ubnt:48v-poe:port8";
gpio-export,output = <0>;
gpios = <&gpio_hc595 14 GPIO_ACTIVE_HIGH>;
};
};
};
&mdio0 {
status = "okay";
phy-mask = <0x10>;
ethernet-switch@1e {
compatible = "brcm,bcm53128";
reg = <0x1e>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port0@0 {
reg = <0>;
label = "lan1";
};
port1@1 {
reg = <1>;
label = "lan2";
};
port2@2 {
reg = <2>;
label = "lan3";
};
port3@3 {
reg = <3>;
label = "lan4";
};
port4@4 {
reg = <4>;
label = "lan5";
};
port5@5 {
reg = <5>;
label = "lan6";
};
port6@6 {
reg = <6>;
label = "lan7";
};
port7@7 {
reg = <7>;
label = "lan8";
};
phy0: port8@8 {
reg = <8>;
label = "cpu";
ethernet = <&eth0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-rxid";
pll-data = <0x16000000 0x00000101 0x00001313>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};