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de79f4ab88
Add patches for 4.14, drop patch 030 since it's already included upstream. Tested on: 1) WRT54GL (with RAM upgraded to 32 MiB) 2) WL500gPv2 (with RAM upgraded to 64 MiB) 3) BCM47186B0 SoC board 4) BCM4706 SoC board Signed-off-by: Paul Wassi <p.wassi@gmx.at> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Wed, 8 Apr 2015 06:58:11 +0200
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Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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If SoC has a CardBus we can set resources of device at slot 1 only. It's
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impossigle to set bridge resources as it simply overwrites device 1
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configuration and usually results in Data bus error-s.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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drivers/ssb/driver_pcicore.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/ssb/driver_pcicore.c
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+++ b/drivers/ssb/driver_pcicore.c
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@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc
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SSB_WARN_ON(!pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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+ /* CardBus SoCs allow configuring dev 1 resources only */
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+ if (extpci_core->cardbusmode && dev != 1 &&
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+ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)
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+ goto out;
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addr = get_cfgspace_addr(pc, bus, dev, func, off);
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if (unlikely(!addr))
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goto out;
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