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https://github.com/openwrt/openwrt.git
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030fc6ab6c
Hardware spec of DIR-842 C1: SoC: QCA9563 DRAM: 128MB DDR2 Flash: 16MB SPI-NOR Switch: QCA8337N WiFi 5.8GHz: QCA9888 WiFi 2.4Ghz: QCA9563 USB: circuit onboard, but components are not soldered Flash instructions: 1. Upgrade the factory.bin through the factory web interface or the u-boot failsafe interface. The firmware will boot up correctly for the first time. Do not power off the device after OpenWrt has booted. Otherwise the u-boot will enter failsafe mode as the checksum of the firmware has been changed. 2. Upgrade the sysupgrade.bin in OpenWrt. After upgrading completes the u-boot won't complain about the firmware checksum and it's OK to use now. 3. If you powered off the device before upgrading the sysupgrade.bin, just upgrade the factory.bin through the u-boot failsafe interface and then goto step 2. Signed-off-by: Jackson Lim <jackcolentern@gmail.com> [fix whitespace issues] Signed-off-by: David Bauer <mail@david-bauer.net>
146 lines
2.3 KiB
Plaintext
146 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "qca956x.dtsi"
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/ {
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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keys {
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compatible = "gpio-keys";
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wps {
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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reset {
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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// Pull up on boot - otherwise the reset button won't work
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reset-button {
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gpio-hog;
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output-high;
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gpios = <11 GPIO_ACTIVE_LOW>;
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line-name = "reset-button";
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};
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};
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&uart {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&spi {
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <30000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x000000 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x040000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "devdata";
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reg = <0x050000 0x10000>;
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read-only;
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};
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partition@60000 {
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label = "devconf";
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reg = <0x060000 0x10000>;
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read-only;
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};
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partition@70000 {
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label = "misc";
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reg = <0x070000 0x10000>;
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read-only;
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};
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partition@80000 {
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compatible = "seama";
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label = "firmware";
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reg = <0x080000 0xf50000>;
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};
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art: partition@fd0000 {
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label = "art";
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reg = <0xfd0000 0x010000>;
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read-only;
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};
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partition@fe0000 {
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label = "reserved";
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reg = <0xfe0000 0x20000>;
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read-only;
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};
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};
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};
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};
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&mdio0 {
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status = "okay";
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phy-mask = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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qca,mib-poll-interval = <500>;
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qca,ar8327-initvals = <
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0x04 0x00080080 /* PORT0 PAD MODE CTRL */
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0x10 0x81000080 /* POWER_ON_STRIP */
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0x50 0xcc35cc35 /* LED_CTRL0 */
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0x54 0xcb37cb37 /* LED_CTRL1 */
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0x58 0x00000000 /* LED_CTRL2 */
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0x5c 0x00f3cf00 /* LED_CTRL3 */
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0x7c 0x0000007e /* PORT0_STATUS */
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>;
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};
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};
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ð0 {
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status = "okay";
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pll-data = <0x03000101 0x00000101 0x00001919>;
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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};
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&wmac {
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status = "okay";
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qca,no-eeprom;
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};
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