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5d3a6fd970
Ran update_kernel.sh in a fresh clone without any existing toolchains. No manual changes needed. Build system: x86_64 Build-tested: bcm27xx/bcm2711 Signed-off-by: John Audia <graysky@archlinux.us>
46 lines
1.4 KiB
Diff
46 lines
1.4 KiB
Diff
From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001
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From: Sander Vanheule <sander@svanheule.net>
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Date: Wed, 3 Feb 2021 10:21:41 +0100
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Subject: MIPS: ralink: manage low reset lines
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Reset lines with indices smaller than 8 are currently considered invalid
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by the rt2880-reset reset controller.
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The MT7621 SoC uses a number of these low reset lines. The DTS defines
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reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2.
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As a result of the above restriction, these resets cannot be asserted or
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de-asserted by the reset controller. In cases where the bootloader does
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not de-assert these lines, this results in e.g. the MT7621's internal
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switch staying in reset.
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Change the reset controller to only ignore the system reset, so all
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reset lines with index greater than 0 are considered valid.
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Signed-off-by: Sander Vanheule <sander@svanheule.net>
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Acked-by: John Crispin <john@phrozen.org>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/ralink/reset.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/ralink/reset.c
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+++ b/arch/mips/ralink/reset.c
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@@ -27,7 +27,7 @@ static int ralink_assert_device(struct r
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{
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u32 val;
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- if (id < 8)
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+ if (id == 0)
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return -1;
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val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
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@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct
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{
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u32 val;
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- if (id < 8)
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+ if (id == 0)
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return -1;
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val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
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