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be2b61e4f1
This option was a spi nor hack which is dropped in commit
bcf4a5f474 ("ramips: remove chunked-io patch and set spi->max_transfer_size instead")
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [edit message]
150 lines
2.4 KiB
Plaintext
150 lines
2.4 KiB
Plaintext
/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "dlink,dir-860l-b1", "mediatek,mt7621-soc";
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model = "D-Link DIR-860L B1";
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aliases {
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led-boot = &led_power_green;
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led-failsafe = &led_power_green;
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led-running = &led_power_green;
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led-upgrade = &led_power_green;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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leds {
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compatible = "gpio-leds";
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power {
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label = "dir-860l-b1:orange:power";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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};
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led_power_green: power2 {
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label = "dir-860l-b1:green:power";
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gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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};
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net {
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label = "dir-860l-b1:orange:net";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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net2 {
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label = "dir-860l-b1:green:net";
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gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x4000>;
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read-only;
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};
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radio: partition@34000 {
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label = "radio";
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reg = <0x34000 0x4000>;
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read-only;
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};
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factory: partition@38000 {
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label = "factory";
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reg = <0x38000 0x8000>;
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read-only;
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};
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partition@40000 {
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label = "defaults";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "seama";
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&radio 0x2000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&pcie1 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&radio 0>;
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci";
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ralink,function = "gpio";
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};
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};
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};
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