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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
75 lines
2.7 KiB
Diff
75 lines
2.7 KiB
Diff
From faca6640521ef0c2fe422533993dd33895f4f7f2 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Wed, 28 Jun 2023 16:24:29 +0100
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Subject: [PATCH 0568/1085] irqchip/irq-brcmstb-l2: Add config for 2711
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controller
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We currently see these regularly:
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[ 25.157560] irq 31, desc: 00000000c15e6d2c, depth: 0, count: 0, unhandled: 0
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[ 25.164658] ->handle_irq(): 00000000b1775675, brcmstb_l2_intc_irq_handle+0x0/0x1a8
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[ 25.172352] ->irq_data.chip(): 00000000fea59f1c, gic_chip_mode1+0x0/0x108
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[ 25.179166] ->action(): 000000003eda6d6f
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[ 25.183096] ->action->handler(): 000000002c09e646, bad_chained_irq+0x0/0x58
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[ 25.190084] IRQ_LEVEL set
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[ 25.193142] IRQ_NOPROBE set
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[ 25.196198] IRQ_NOREQUEST set
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[ 25.199255] IRQ_NOTHREAD set
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with:
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$ cat /proc/interrupts | grep 31:
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31: 1 0 0 0 GICv2 129 Level (null)
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The interrupt is described in DT with IRQ_TYPE_LEVEL_HIGH
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But the current compatible string uses the controller in edge triggered mode
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(as that config matches our register layout).
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Add a new compatible structure for level driven interrupt with our register layout.
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We had already been using this compatible string in device tree, so no change needed
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there.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/irqchip/irq-brcmstb-l2.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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--- a/drivers/irqchip/irq-brcmstb-l2.c
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+++ b/drivers/irqchip/irq-brcmstb-l2.c
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@@ -51,6 +51,16 @@ static const struct brcmstb_intc_init_pa
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.cpu_mask_clear = 0x0C
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};
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+/* Register offsets in the 2711 L2 level interrupt controller */
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+static const struct brcmstb_intc_init_params l2_2711_lvl_intc_init = {
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+ .handler = handle_level_irq,
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+ .cpu_status = 0x00,
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+ .cpu_clear = 0x08,
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+ .cpu_mask_status = 0x0c,
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+ .cpu_mask_set = 0x10,
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+ .cpu_mask_clear = 0x14
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+};
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+
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/* L2 intc private data structure */
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struct brcmstb_l2_intc_data {
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struct irq_domain *domain;
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@@ -288,11 +298,18 @@ static int __init brcmstb_l2_lvl_intc_of
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return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
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}
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+static int __init brcmstb_l2_2711_lvl_intc_of_init(struct device_node *np,
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+ struct device_node *parent)
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+{
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+ return brcmstb_l2_intc_of_init(np, parent, &l2_2711_lvl_intc_init);
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+}
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+
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IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
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IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
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IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
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IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
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IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
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+IRQCHIP_MATCH("brcm,bcm2711-l2-intc", brcmstb_l2_2711_lvl_intc_of_init)
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IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
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MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
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MODULE_LICENSE("GPL v2");
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