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On some but not all devices using the RTL8221B 2.5GBit/s PHY the SerDes setup sequence may hang under some circumstances (eg. <2500M link partner present during boot). RTL8221B-VB-CG 2.5Gbps PHY (C45) mdio-bus:01: rtl822xb_config_init failed: -110 Work-around the issue by performing a hardware reset and subsequent retry of the SerDes setup, which seems to always succeed. Doing this requires moving ALDPS setup to config_init (which is anyway the better place for that) as it otherwise doesn't survive the reset. Also disable listening on MDIO address 0 which may be used by other PHYs despite being spec'ed as "broadcast address", as bus activity on address 0 may otherwise confuse the RealTek PHY for good reasons. Tested-by: Luis Mita <luis@luismita.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> (cherry picked from commit c87a767801ef375feadb0a5c41d5a674ad3a7d2c) Link: https://github.com/openwrt/openwrt/pull/17790 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
43 lines
1.4 KiB
Diff
43 lines
1.4 KiB
Diff
From 9155098547fb1172d4fa536f3f6bc9d42f59d08c Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sat, 22 Apr 2023 03:26:01 +0100
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Subject: [PATCH] net: phy: realtek: setup ALDPS on RTL822x
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Setup Link Down Power Saving Mode according the DTS property
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just like for RTL821x 1GE PHYs.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/phy/realtek/realtek_main.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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--- a/drivers/net/phy/realtek/realtek_main.c
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+++ b/drivers/net/phy/realtek/realtek_main.c
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@@ -82,6 +82,10 @@
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#define RTL822X_VND2_GANLPAR 0xa414
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+#define RTL8221B_PHYCR1 0xa430
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+#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
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+#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -889,6 +893,15 @@ static int rtl822xb_config_init(struct p
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if (ret < 0)
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return ret;
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+ if (of_property_read_bool(phydev->mdio.dev.of_node, "realtek,aldps-enable"))
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+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
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+ RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
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+ else
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+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
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+ RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
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+ if (ret < 0)
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+ return ret;
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+
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/* Disable SGMII AN */
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x7588, 0x2);
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if (ret < 0)
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