mirror of
https://github.com/openwrt/openwrt.git
synced 2025-01-18 18:56:37 +00:00
f22febae1a
Some checks are pending
Build Kernel / Build all affected Kernels (push) Waiting to run
Add pending PCI patch that should correctly fix mediatek driver with Airoha SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
59 lines
2.2 KiB
Diff
59 lines
2.2 KiB
Diff
From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001
|
|
Message-ID: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
|
|
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Date: Wed, 8 Jan 2025 10:50:40 +0100
|
|
Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in
|
|
mtk_pcie_en7581_power_up()
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Replace clk_bulk_prepare() and clk_bulk_enable() with
|
|
clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine.
|
|
|
|
Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org
|
|
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
|
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
---
|
|
drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++-----------
|
|
1 file changed, 3 insertions(+), 11 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
|
|
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
|
|
@@ -907,12 +907,6 @@ static int mtk_pcie_en7581_power_up(stru
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
|
|
- err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
|
|
- if (err) {
|
|
- dev_err(dev, "failed to prepare clock\n");
|
|
- goto err_clk_prepare;
|
|
- }
|
|
-
|
|
val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
|
|
FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
|
|
FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
|
|
@@ -925,17 +919,15 @@ static int mtk_pcie_en7581_power_up(stru
|
|
FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
|
|
writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
|
|
|
|
- err = clk_bulk_enable(pcie->num_clks, pcie->clks);
|
|
+ err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
|
|
if (err) {
|
|
dev_err(dev, "failed to prepare clock\n");
|
|
- goto err_clk_enable;
|
|
+ goto err_clk_prepare_enable;
|
|
}
|
|
|
|
return 0;
|
|
|
|
-err_clk_enable:
|
|
- clk_bulk_unprepare(pcie->num_clks, pcie->clks);
|
|
-err_clk_prepare:
|
|
+err_clk_prepare_enable:
|
|
pm_runtime_put_sync(dev);
|
|
pm_runtime_disable(dev);
|
|
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|