From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 19 Nov 2020 17:43:11 +0200 Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain Signed-off-by: Eugen Hristev Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd --- drivers/clk/at91/sama7g5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -775,13 +775,13 @@ static const struct clk_pll_characterist /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { .output = { .min = 140000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3 }, + .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; /* MCK0 layout. */ static const struct clk_master_layout mck0_layout = { - .mask = 0x373, + .mask = 0x773, .pres_shift = 4, .offset = 0x28, };