// SPDX-License-Identifier: GPL-2.0-or-later

/dts-v1/;

#include <dt-bindings/clock/bcm63268-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/reset/bcm63268-reset.h>
#include <dt-bindings/soc/bcm63268-pm.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm63268";

	aliases {
		nflash = &nflash;
		pinctrl = &pinctrl;
		serial0 = &uart0;
		serial1 = &uart1;
		spi0 = &lsspi;
		spi1 = &hsspi;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	clocks {
		periph_osc: periph-osc {
			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};

		hsspi_osc: hsspi-osc {
			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <400000000>;
			clock-output-names = "hsspi_osc";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		mips-hpt-frequency = <200000000>;

		cpu@0 {
			compatible = "brcm,bmips4350", "mips,mips4Kc";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,bmips4350", "mips,mips4Kc";
			device_type = "cpu";
			reg = <1>;
		};
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0>;
	};

	ubus {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "simple-bus";
		ranges;

		periph_clk: clock-controller@10000004 {
			compatible = "brcm,bcm63268-clocks";
			reg = <0x10000004 0x4>;
			#clock-cells = <1>;
		};

		pll_cntl: syscon@10000008 {
			compatible = "syscon", "simple-mfd";
			reg = <0x10000008 0x4>;
			native-endian;

			syscon-reboot {
				compatible = "syscon-reboot";
				offset = <0x0>;
				mask = <0x1>;
			};
		};

		periph_rst: reset-controller@10000010 {
			compatible = "brcm,bcm6345-reset";
			reg = <0x10000010 0x4>;
			#reset-cells = <1>;
		};

		ext_intc: interrupt-controller@10000018 {
			#address-cells = <1>;
			compatible = "brcm,bcm6345-ext-intc";
			reg = <0x10000018 0x4>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_EXT0>,
				     <BCM63268_IRQ_EXT1>,
				     <BCM63268_IRQ_EXT2>,
				     <BCM63268_IRQ_EXT3>;
		};

		periph_intc: interrupt-controller@10000020 {
			#address-cells = <1>;
			compatible = "brcm,bcm6345-l1-intc";
			reg = <0x10000020 0x20>,
			      <0x10000040 0x20>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>, <3>;
		};

		wdt: watchdog@1000009c {
			compatible = "brcm,bcm7038-wdt";
			reg = <0x1000009c 0xc>;

			clocks = <&periph_osc>;

			timeout-sec = <30>;
		};

		timer_clk: clock-controller@100000ac {
			compatible = "brcm,bcm63268-timer-clocks";
			reg = <0x100000ac 0x4>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		gpio_cntl: syscon@100000c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "brcm,bcm63268-gpio-sysctl",
				     "syscon", "simple-mfd";
			reg = <0x100000c0 0x80>;
			ranges = <0 0x100000c0 0x80>;
			native-endian;

			gpio: gpio@0 {
				compatible = "brcm,bcm63268-gpio";
				reg-names = "dirout", "dat";
				reg = <0x0 0x8>, <0x8 0x8>;

				gpio-controller;
				gpio-ranges = <&pinctrl 0 0 52>;
				#gpio-cells = <2>;
			};

			pinctrl: pinctrl@10 {
				compatible = "brcm,bcm63268-pinctrl";
				reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;

				pinctrl_serial_led: serial_led-pins {
					pinctrl_serial_led_clk: serial_led_clk-pins {
						function = "serial_led_clk";
						pins = "gpio0";
					};

					pinctrl_serial_led_data: serial_led_data-pins {
						function = "serial_led_data";
						pins = "gpio1";
					};
				};

				pinctrl_hsspi_cs4: hsspi_cs4-pins {
					function = "hsspi_cs4";
					pins = "gpio16";
				};

				pinctrl_hsspi_cs5: hsspi_cs5-pins {
					function = "hsspi_cs5";
					pins = "gpio17";
				};

				pinctrl_hsspi_cs6: hsspi_cs6-pins {
					function = "hsspi_cs6";
					pins = "gpio8";
				};

				pinctrl_hsspi_cs7: hsspi_cs7-pins {
					function = "hsspi_cs7";
					pins = "gpio9";
				};

				pinctrl_adsl_spi: adsl_spi {
					pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
						function = "adsl_spi_miso";
						pins = "gpio18";
					};

					pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
						function = "adsl_spi_mosi";
						pins = "gpio19";
					};
				};

				pinctrl_vreq_clk: vreq_clk-pins {
					function = "vreq_clk";
					pins = "gpio22";
				};

				pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
					function = "pcie_clkreq_b";
					pins = "gpio23";
				};

				pinctrl_robosw_led_clk: robosw_led_clk-pins {
					function = "robosw_led_clk";
					pins = "gpio30";
				};

				pinctrl_robosw_led_data: robosw_led_data-pins {
					function = "robosw_led_data";
					pins = "gpio31";
				};

				pinctrl_nand: nand-pins {
					function = "nand";
					pins = "nand_grp";
				};

				pinctrl_gpio35_alt: gpio35_alt-pins {
					function = "gpio35_alt";
					pin = "gpio35";
				};

				pinctrl_dectpd: dectpd-pins {
					function = "dectpd";
					pins = "dectpd_grp";
				};

				pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
					function = "vdsl_phy_override_0";
					pins = "vdsl_phy_override_0_grp";
				};

				pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
					function = "vdsl_phy_override_1";
					pins = "vdsl_phy_override_1_grp";
				};

				pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
					function = "vdsl_phy_override_2";
					pins = "vdsl_phy_override_2_grp";
				};

				pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
					function = "vdsl_phy_override_3";
					pins = "vdsl_phy_override_3_grp";
				};

				pinctrl_dsl_gpio8: dsl_gpio8-pins {
					function = "dsl_gpio8";
					pins = "dsl_gpio8";
				};

				pinctrl_dsl_gpio9: dsl_gpio9-pins {
					function = "dsl_gpio9";
					pins = "dsl_gpio9";
				};
			};
		};

		uart0: serial@10000180 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x10000180 0x18>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_UART0>;

			clocks = <&periph_osc>;
			clock-names = "periph";

			status = "disabled";
		};

		uart1: serial@100001a0 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x100001a0 0x18>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_UART1>;

			clocks = <&periph_osc>;
			clock-names = "periph";

			status = "disabled";
		};

		nflash: nand@10000200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm6368",
				     "brcm,brcmnand-v4.0",
				     "brcm,brcmnand";
			reg = <0x10000200 0x180>,
			      <0x10000600 0x200>,
			      <0x100000b0 0x10>;
			reg-names = "nand",
				    "nand-cache",
				    "nand-int-base";

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_NAND>;

			clocks = <&periph_clk BCM63268_CLK_NAND>;
			clock-names = "nand";

			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;

			status = "disabled";
		};

		lsspi: spi@10000800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,bcm6358-spi";
			reg = <0x10000800 0x70c>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_LSSPI>;

			clocks = <&periph_clk BCM63268_CLK_SPI>;
			clock-names = "spi";

			resets = <&periph_rst BCM63268_RST_SPI>;

			status = "disabled";
		};

		hsspi: spi@10001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,bcm6328-hsspi";
			reg = <0x10001000 0x600>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_HSSPI>;

			clocks = <&periph_clk BCM63268_CLK_HSSPI>,
				 <&hsspi_osc>;
			clock-names = "hsspi",
				      "pll";

			resets = <&periph_rst BCM63268_RST_SPI>;

			status = "disabled";
		};

		serdes_cntl: syscon@10001804 {
			compatible = "syscon";
			reg = <0x10001804 0x4>;
			native-endian;
		};

		periph_pwr: power-controller@1000184c {
			compatible = "brcm,bcm63268-power-controller";
			reg = <0x1000184c 0x4>;
			#power-domain-cells = <1>;
		};

		leds: led-controller@10001900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,bcm6328-leds";
			reg = <0x10001900 0x24>;

			status = "disabled";
		};

		ehci: usb@10002500 {
			compatible = "brcm,bcm63268-ehci", "generic-ehci";
			reg = <0x10002500 0x100>;
			big-endian;
			spurious-oc;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_EHCI>;

			phys = <&usbh 0>;
			phy-names = "usb";

			status = "disabled";
		};

		ohci: usb@10002600 {
			compatible = "brcm,bcm63268-ohci", "generic-ohci";
			reg = <0x10002600 0x100>;
			big-endian;
			no-big-frame-no;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_OHCI>;

			phys = <&usbh 0>;
			phy-names = "usb";

			status = "disabled";
		};

		usbh: usb-phy@10002700 {
			compatible = "brcm,bcm63268-usbh-phy";
			reg = <0x10002700 0x38>;

			#phy-cells = <1>;

			clocks = <&periph_clk BCM63268_CLK_USBH>,
				 <&timer_clk BCM63268_TCLK_USB_REF>;
			clock-names = "usbh",
				      "usb_ref";

			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
			resets = <&periph_rst BCM63268_RST_USBH>;

			status = "disabled";
		};

		random: rng@10002880 {
			compatible = "brcm,bcm6368-rng";
			reg = <0x10002880 0x14>;

			clocks = <&periph_clk BCM63268_CLK_IPSEC>;
			clock-names = "ipsec";

			resets = <&periph_rst BCM63268_RST_IPSEC>;

			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_IPSEC>;
		};

		ethernet: ethernet@1000d800 {
			compatible = "brcm,bcm63268-enetsw";
			reg = <0x1000d800 0x80>,
			      <0x1000da00 0x80>,
			      <0x1000dc00 0x80>;
			reg-names = "dma",
				    "dma-channels",
				    "dma-sram";

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
				     <BCM63268_IRQ_ENETSW_TX_DMA0>;
			interrupt-names = "rx",
					  "tx";

			clocks = <&periph_clk BCM63268_CLK_GMAC>,
				 <&periph_clk BCM63268_CLK_ROBOSW>,
				 <&periph_clk BCM63268_CLK_ROBOSW250>,
				 <&timer_clk BCM63268_TCLK_EPHY1>,
				 <&timer_clk BCM63268_TCLK_EPHY2>,
				 <&timer_clk BCM63268_TCLK_EPHY3>,
				 <&timer_clk BCM63268_TCLK_GPHY1>;

			resets = <&periph_rst BCM63268_RST_ENETSW>,
				 <&periph_rst BCM63268_RST_EPHY>,
				 <&periph_rst BCM63268_RST_GPHY>;

			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;

			dma-rx = <0>;
			dma-tx = <1>;

			status = "disabled";
		};

		pcie: pcie@106e0000 {
			compatible = "brcm,bcm6328-pcie";
			reg = <0x106e0000 0x10000>;
			#address-cells = <3>;
			#size-cells = <2>;

			device_type = "pci";
			bus-range = <0x00 0x01>;
			ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
			linux,pci-probe-only = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <BCM63268_IRQ_PCIE_RC>;

			clocks = <&periph_clk BCM63268_CLK_PCIE>;
			clock-names = "pcie";

			resets = <&periph_rst BCM63268_RST_PCIE>,
				 <&periph_rst BCM63268_RST_PCIE_EXT>,
				 <&periph_rst BCM63268_RST_PCIE_CORE>,
				 <&periph_rst BCM63268_RST_PCIE_HARD>;
			reset-names = "pcie",
				      "pcie-ext",
				      "pcie-core",
				      "pcie-hard";

			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;

			brcm,serdes = <&serdes_cntl>;

			status = "disabled";
		};

		switch0: switch@10700000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,bcm63268-switch";
			reg = <0x10700000 0x8000>;
			big-endian;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@8 {
					reg = <8>;

					phy-mode = "internal";
					ethernet = <&ethernet>;

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};

		mdio: mdio@107000b0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,bcm6368-mdio-mux";
			reg = <0x107000b0 0x8>;

			mdio_int: mdio@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				phy1: ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <2>;
				};

				phy3: ethernet-phy@3 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <3>;
				};

				phy4: ethernet-phy@4 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <4>;
				};
			};

			mdio_ext: mdio@1 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <1>;
			};
		};
	};
};