From c225b48d2cf5f5a824b5b0a4144511bdc5f65ab5 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 14 Aug 2022 11:18:11 -0500
Subject: [PATCH 080/117] riscv: dts: allwinner: d1: Add thermal sensor and
 zone

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 .../sun20i-d1-common-regulators.dtsi          |  4 ++
 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 41 +++++++++++++++++++
 2 files changed, 45 insertions(+)

--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
@@ -49,3 +49,7 @@
 	regulator-max-microvolt = <1800000>;
 	ldo-in-supply = <&reg_vcc_3v3>;
 };
+
+&ths {
+	vref-supply = <&reg_aldo>;
+};
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
@@ -59,6 +59,35 @@
 		#clock-cells = <0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <0>;
+			polling-delay-passive = <0>;
+			thermal-sensors = <&ths>;
+
+			trips {
+				cpu_target: cpu-target {
+					hysteresis = <3000>;
+					temperature = <85000>;
+					type = "passive";
+				};
+
+				cpu-crit {
+					hysteresis = <0>;
+					temperature = <110000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_target>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
@@ -252,6 +281,18 @@
 			#size-cells = <0>;
 		};
 
+		ths: temperature-sensor@2009400 {
+			compatible = "allwinner,sun20i-d1-ths";
+			reg = <0x2009400 0x400>;
+			interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_THS>;
+			nvmem-cells = <&ths_calib>;
+			nvmem-cell-names = "calibration";
+			#thermal-sensor-cells = <0>;
+		};
+
 		lradc: keys@2009800 {
 			compatible = "allwinner,sun20i-d1-lradc",
 				     "allwinner,sun50i-r329-lradc";