From 8fc2a02d1d2e98a01a2dad3bf3da8e33366725eb Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 7 Aug 2022 19:17:35 -0500 Subject: [PATCH 111/117] drm: panel: cwd686: Use vendor panel init sequence Signed-off-by: Samuel Holland --- .../gpu/drm/panel/panel-clockwork-cwd686.c | 142 ++++-------------- 1 file changed, 32 insertions(+), 110 deletions(-) --- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c +++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c @@ -47,10 +47,12 @@ static inline struct cwd686 *panel_to_cw return container_of(panel, struct cwd686, panel); } -#define ICNL9707_DCS(seq...) \ +#define dcs_write_seq(seq...) \ ({ \ static const u8 d[] = { seq }; \ - mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \ + ssize_t r = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \ + if (r < 0) \ + return r; \ }) #define ICNL9707_CMD_CGOUTL 0xB3 @@ -128,115 +130,35 @@ static inline struct cwd686 *panel_to_cw static int cwd686_init_sequence(struct cwd686 *ctx) { struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int err; - /* Enable access to Level 2 registers */ - ICNL9707_DCS(ICNL9707_CMD_PASSWORD1, - ICNL9707_P_PASSWORD1_ENABLE_LVL2, - ICNL9707_P_PASSWORD1_ENABLE_LVL2); - ICNL9707_DCS(ICNL9707_CMD_PASSWORD2, - ICNL9707_P_PASSWORD2_ENABLE_LVL2, - ICNL9707_P_PASSWORD2_ENABLE_LVL2); - - /* Set PWRCON_VCOM (-0.495V, -0.495V) */ - ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM, - ICNL9707_P_PWRCON_VCOM_0495V, - ICNL9707_P_PWRCON_VCOM_0495V); - - /* Map ASG output signals */ - ICNL9707_DCS(ICNL9707_CMD_CGOUTR, - ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5, - ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5, - ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3); - ICNL9707_DCS(ICNL9707_CMD_CGOUTL, - ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6, - ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6, - ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND, - ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4); - - /* Undocumented commands provided by the vendor */ - ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01); - ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01); - ICNL9707_DCS(0xB2, 0x73); - - ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG, - 0x4E, 0x0E, 0x50, 0x50, 0x26, - 0x1D, 0x00, 0x14, 0x42, 0x03); - ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ, - 0x01, 0x01, 0x09, 0x11, 0x0D, 0x55, - 0x19, 0x19, 0x21, 0x1D, 0x00, 0x00, - 0x00, 0x00, 0x02, 0xFF, 0x3C); - ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63); - - /* Disable abnormal power-off flag */ - ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44); - - ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63); - - /* Set VBP, VFP, VSW, HBP, HFP, HSW */ - ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04); - - /* Set resolution */ - ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41); - - /* Set frame blanking */ - ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04); - - ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00); - - /* Another undocumented command */ - ICNL9707_DCS(0xC5, 0x00); - - ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF); - - /* Another set of undocumented commands */ - ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88); - ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07); - - /* Set Gamma to 2.2 */ - ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA, - 0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B, - 0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57, - 0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A, - 0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D, - 0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48, - 0x3B, 0x2A, 0x06); - - ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00); - - /* Another undocumented command */ - ICNL9707_DCS(0xF4, 0x08, 0x77); - - ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE, - ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH); - - /* Enable tearing mode at VBLANK */ - err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (err) { - dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err); - return err; - } - - /* Disable access to Level 2 registers */ - ICNL9707_DCS(ICNL9707_CMD_PASSWORD2, - ICNL9707_P_PASSWORD2_DEFAULT, - ICNL9707_P_PASSWORD2_DEFAULT); - ICNL9707_DCS(ICNL9707_CMD_PASSWORD1, - ICNL9707_P_PASSWORD1_DEFAULT, - ICNL9707_P_PASSWORD1_DEFAULT); + dcs_write_seq(0xF0,0x5A,0x5A); + dcs_write_seq(0xF1,0xA5,0xA5); + dcs_write_seq(0xB6,0x0D,0x0D); + dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06); + dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07); + dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01); + dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01); + dcs_write_seq(0xB2,0x73); + dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03); + dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C); + dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63); + dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44); + dcs_write_seq(0xBA,0x12,0x63); + dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04); + dcs_write_seq(0xC2,0x11,0x41); + dcs_write_seq(0xC3,0x22,0x31,0x04); + dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00); + dcs_write_seq(0xC5,0x00); + dcs_write_seq(0xD0,0x37,0xFF,0xFF); + dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88); + dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07); + dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2 + dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00); + dcs_write_seq(0xF4,0x08,0x77); + dcs_write_seq(0x36,0x14); + dcs_write_seq(0x35,0x00); + dcs_write_seq(0xF1,0x5A,0x5A); + dcs_write_seq(0xF0,0xA5,0xA5); return 0; }