From b477a1a53553336edcfeb83be1b35817928daed8 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Mon, 5 Jun 2023 14:46:16 +0800 Subject: [PATCH 084/116] dt-binding: media: Add JH7110 Camera Subsystem. Add the bindings documentation for Starfive JH7110 Camera Subsystem which is used for handing image sensor data. Signed-off-by: Changhuang Liang Signed-off-by: Jack Zhu --- .../bindings/media/starfive,jh7110-camss.yaml | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml --- /dev/null +++ b/Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Starfive SoC CAMSS ISP + +maintainers: + - Jack Zhu + - Changhuang Liang + +description: + The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It + consists of a VIN controller (Video In Controller, a top-level control unit) + and an ISP. + +properties: + compatible: + const: starfive,jh7110-vin + + reg: + maxItems: 8 + + reg-names: + items: + - const: csi2rx + - const: vclk + - const: vrst + - const: sctrl + - const: isp + - const: trst + - const: pmu + - const: syscrg + + clocks: + maxItems: 16 + + clock-names: + items: + - const: clk_apb_func + - const: clk_pclk + - const: clk_sys_clk + - const: clk_wrapper_clk_c + - const: clk_dvp_inv + - const: clk_axiwr + - const: clk_mipi_rx0_pxl + - const: clk_pixel_clk_if0 + - const: clk_pixel_clk_if1 + - const: clk_pixel_clk_if2 + - const: clk_pixel_clk_if3 + - const: clk_m31dphy_cfgclk_in + - const: clk_m31dphy_refclk_in + - const: clk_m31dphy_txclkesc_lan0 + - const: clk_ispcore_2x + - const: clk_isp_axi + + resets: + maxItems: 14 + + reset-names: + items: + - const: rst_wrapper_p + - const: rst_wrapper_c + - const: rst_pclk + - const: rst_sys_clk + - const: rst_axird + - const: rst_axiwr + - const: rst_pixel_clk_if0 + - const: rst_pixel_clk_if1 + - const: rst_pixel_clk_if2 + - const: rst_pixel_clk_if3 + - const: rst_m31dphy_hw + - const: rst_m31dphy_b09_always_on + - const: rst_isp_top_n + - const: rst_isp_top_axi + + power-domains: + items: + - description: JH7110 ISP Power Domain Switch Controller. + + interrupts: + maxItems: 5 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port for receiving DVP data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [5, 6] + + bus-width: + enum: [8, 10, 12] + + data-shift: + enum: [0, 2] + default: 0 + + hsync-active: + enum: [0, 1] + default: 1 + + vsync-active: + enum: [0, 1] + default: 1 + + required: + - bus-type + - bus-width + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Input port for receiving CSI data. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - interrupts + - ports + +additionalProperties: false + +examples: + - | + vin_sysctl: vin_sysctl@19800000 { + compatible = "starfive,jh7110-vin"; + reg = <0x0 0x19800000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x19820000 0x0 0x10000>, + <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>, + <0x0 0x11840000 0x0 0x10000>, + <0x0 0x17030000 0x0 0x10000>, + <0x0 0x13020000 0x0 0x10000>; + reg-names = "csi2rx", "vclk", "vrst", "sctrl", + "isp", "trst", "pmu", "syscrg"; + clocks = <&clkisp JH7110_DOM4_APB_FUNC>, + <&clkisp JH7110_U0_VIN_PCLK>, + <&clkisp JH7110_U0_VIN_SYS_CLK>, + <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>, + <&clkisp JH7110_DVP_INV>, + <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>, + <&clkisp JH7110_MIPI_RX0_PXL>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>, + <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>, + <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>, + <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>, + <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>, + <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>; + clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk", + "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", + "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", + "clk_pixel_clk_if1", "clk_pixel_clk_if2", + "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in", + "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0", + "clk_ispcore_2x", "clk_isp_axi"; + resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>, + <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>, + <&rstgen RSTN_U0_VIN_N_PCLK>, + <&rstgen RSTN_U0_VIN_N_SYS_CLK>, + <&rstgen RSTN_U0_VIN_P_AXIRD>, + <&rstgen RSTN_U0_VIN_P_AXIWR>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>, + <&rstgen RSTN_U0_M31DPHY_HW>, + <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>, + <&rstgen RSTN_U0_DOM_ISP_TOP_N>, + <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>; + reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", + "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0", + "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3", + "rst_m31dphy_hw", "rst_m31dphy_b09_always_on", + "rst_isp_top_n", "rst_isp_top_axi"; + starfive,aon-syscon = <&aon_syscon 0x00>; + power-domains = <&pwrc JH7110_PD_ISP>; + /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */ + interrupts = <92>, <87>, <88>, <89>, <90>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vin_from_sc2235: endpoint { + remote-endpoint = <&sc2235_to_vin>; + bus-type = <5>; + bus-width = <8>; + data-shift = <2>; + hsync-active = <1>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + vin_from_csi2rx: endpoint { + remote-endpoint = <&csi2rx_to_vin>; + }; + }; + }; + };