// SPDX-License-Identifier: GPL-2.0-or-later OR MIT #include "ar9344.dtsi" #include #include / { keys { compatible = "gpio-keys"; reset { linux,code = ; gpios = <&gpio 17 GPIO_ACTIVE_LOW>; debounce-interval = <60>; }; wps { linux,code = ; gpios = <&gpio 16 GPIO_ACTIVE_LOW>; debounce-interval = <60>; }; }; }; ð0 { status = "okay"; /* default for ar934x, except for 1000M */ pll-data = <0x06000000 0x00000101 0x00001616>; phy-mode = "rgmii"; phy-handle = <&phy0>; }; &mdio0 { status = "okay"; phy0: ethernet-phy@0 { reg = <0>; qca,ar8327-initvals = < /* GPL code drop (bsp.h & athrs17_phy.c) */ 0x10 0xc1000000 /* PWS_REG_VALUE */ 0x04 0x07600000 /* PORT0 PAD Mode */ 0x0c 0x01000000 /* PORT6 PAD Mode */ 0x7c 0x0000007e /* PORT0_STATUS */ 0x94 0x0000007e /* PORT6_STATUS */ >; }; }; &pcie { status = "okay"; ath9k: wifi@0,0 { compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; qca,no-eeprom; gpio-controller; #gpio-cells = <2>; }; }; &ref { clock-frequency = <40000000>; }; &spi { status = "okay"; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "uboot"; reg = <0x000000 0x010000>; read-only; }; partition@10000 { label = "nvram"; reg = <0x010000 0x010000>; read-only; }; partition@20000 { label = "firmware"; reg = <0x020000 0xF90000>; compatible = "denx,uimage"; }; partition@fb0000 { label = "lang"; reg = <0xfb0000 0x030000>; read-only; }; partition@fe0000 { label = "mac"; reg = <0xfe0000 0x010000>; read-only; }; partition@ff0000 { label = "art"; reg = <0xff0000 0x010000>; read-only; }; }; }; }; &usb { status = "okay"; #address-cells = <1>; #size-cells = <0>; hub_port1: port@1 { reg = <1>; #trigger-source-cells = <0>; }; }; &usb_phy { status = "okay"; }; &wmac { status = "okay"; qca,no-eeprom; };