--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -1,7 +1,6 @@
 /*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <ming.huang@mediatek.com>
- *	   Sean Wang <sean.wang@mediatek.com>
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
  *
  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  */
@@ -24,7 +23,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
 	};
 
 	cpus {
@@ -45,18 +44,18 @@
 		key-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
-			gpios = <&pio 0 0>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		key-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 102 0>;
+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
 		};
 	};
 
 	memory {
-		reg = <0 0x40000000 0 0x20000000>;
+		reg = <0 0x40000000 0 0x40000000>;
 	};
 
 	reg_1p8v: regulator-1p8v {
@@ -132,22 +131,22 @@
 
 				port@0 {
 					reg = <0>;
-					label = "lan0";
+					label = "lan1";
 				};
 
 				port@1 {
 					reg = <1>;
-					label = "lan1";
+					label = "lan2";
 				};
 
 				port@2 {
 					reg = <2>;
-					label = "lan2";
+					label = "lan3";
 				};
 
 				port@3 {
 					reg = <3>;
-					label = "lan3";
+					label = "lan4";
 				};
 
 				port@4 {
@@ -240,7 +239,22 @@
 	status = "okay";
 };
 
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
 &pio {
+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
+	 */
+	asm_sel {
+		gpio-hog;
+		gpios = <90 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+
 	/* eMMC is shared pin with parallel NAND */
 	emmc_pins_default: emmc-pins-default {
 		mux {
@@ -517,11 +531,11 @@
 };
 
 &sata {
-	status = "okay";
+	status = "disabled";
 };
 
 &sata_phy {
-	status = "okay";
+	status = "disabled";
 };
 
 &spi0 {