From d3c267836e424c9246a4b174d9bd024cb0f656b4 Mon Sep 17 00:00:00 2001 From: Dom Cobley Date: Tue, 17 May 2022 12:46:42 +0100 Subject: [PATCH] drm/vc4: hdmi: Add more checks for 4k resolutions At least the 4096x2160@60Hz mode requires some overclocking that isn't available by default, even if hdmi_enable_4kp60 is enabled. Let's add some logic to detect whether we can satisfy the core clock requirements for that mode, and prevent it from being used otherwise. Signed-off-by: Dom Cobley Reviewed-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_drv.h | 6 ++++++ drivers/gpu/drm/vc4/vc4_hdmi.c | 11 +++++++++-- drivers/gpu/drm/vc4/vc4_hvs.c | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-) --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -352,6 +352,12 @@ struct vc4_hvs { * available. */ bool vc5_hdmi_enable_hdmi_20; + + /* + * 4096x2160@60 requires a core overclock to work, so register + * whether that is sufficient. + */ + bool vc5_hdmi_enable_4096by2160; }; struct vc4_plane { --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1976,6 +1976,7 @@ vc4_hdmi_sink_supports_format_bpc(const static enum drm_mode_status vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, + const struct drm_display_mode *mode, unsigned long long clock) { const struct drm_connector *connector = &vc4_hdmi->connector; @@ -1988,6 +1989,12 @@ vc4_hdmi_encoder_clock_valid(const struc if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) return MODE_CLOCK_HIGH; + /* 4096x2160@60 is not reliable without overclocking core */ + if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && + mode->hdisplay > 3840 && mode->vdisplay >= 2160 && + drm_mode_vrefresh(mode) >= 50) + return MODE_CLOCK_HIGH; + if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) return MODE_CLOCK_HIGH; @@ -2022,7 +2029,7 @@ vc4_hdmi_encoder_compute_clock(const str unsigned long long clock; clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); - if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) + if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) return -EINVAL; vc4_state->tmds_char_rate = clock; @@ -2185,7 +2192,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e (mode->hsync_end % 2) || (mode->htotal % 2))) return MODE_H_ILLEGAL; - return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); + return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); } static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -1060,6 +1060,9 @@ static int vc4_hvs_bind(struct device *d if (max_rate >= 550000000) hvs->vc5_hdmi_enable_hdmi_20 = true; + if (max_rate >= 600000000) + hvs->vc5_hdmi_enable_4096by2160 = true; + hvs->max_core_rate = max_rate; ret = clk_prepare_enable(hvs->core_clk);