// SPDX-License-Identifier: GPL-2.0-or-later OR MIT #include #include #include #include "rtl838x.dtsi" / { compatible = "linksys,lgs310c", "realtek,rtl838x-soc"; model = "Linksys LGS310C"; aliases { led-boot = &led_power; led-failsafe = &led_fault; led-running = &led_power; led-upgrade = &led_power; }; memory@0 { device_type = "memory"; reg = <0x0 0x10000000>; }; leds: leds { pinctrl-names = "default"; pinctrl-0 = <&pinmux_disable_sys_led>; compatible = "gpio-leds"; led_power: led-0 { function = LED_FUNCTION_POWER; color = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; led_fault: led-1 { function = LED_FUNCTION_FAULT; color = ; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; }; /* i2c of the left SFP cage: port 9 */ i2c0: i2c-gpio-0 { compatible = "i2c-gpio"; sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; }; sfp0: sfp-p9 { compatible = "sff,sfp"; i2c-bus = <&i2c0>; los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; /* i2c of the right SFP cage: port 10 */ i2c1: i2c-gpio-1 { compatible = "i2c-gpio"; sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* * ports 9 & 10 use a shared SCL, and are currently not usable in parallel * So for now disable the SCL on the second port. * * scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; */ i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; }; sfp1: sfp-p10 { compatible = "sff,sfp"; i2c-bus = <&i2c1>; los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; keys { compatible = "gpio-keys"; reset { label = "reset"; gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; linux,code = ; }; }; gpio1: rtl8231-gpio { compatible = "realtek,rtl8231-gpio"; #gpio-cells = <2>; gpio-controller; indirect-access-bus-id = <0>; }; }; &spi0 { status = "okay"; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x00000000 0x80000>; read-only; }; partition@80000 { label = "u-boot-env"; reg = <0x00080000 0x10000>; }; partition@90000 { label = "u-boot-env2"; reg = <0x00090000 0x10000>; }; partition@a0000 { label = "jffs2"; reg = <0x000a0000 0x500000>; }; partition@5a0000 { label = "firmware"; compatible = "openwrt,uimage"; reg = <0x005a0000 0xd30000>; }; partition@2d0000 { label = "kernel2"; reg = <0x012d0000 0xd30000>; }; }; }; }; &uart1 { status = "okay"; }; ðernet0 { mdio: mdio-bus { compatible = "realtek,rtl838x-mdio"; regmap = <ðernet0>; #address-cells = <1>; #size-cells = <0>; INTERNAL_PHY(8) INTERNAL_PHY(9) INTERNAL_PHY(10) INTERNAL_PHY(11) INTERNAL_PHY(12) INTERNAL_PHY(13) INTERNAL_PHY(14) INTERNAL_PHY(15) INTERNAL_PHY(24) INTERNAL_PHY(26) }; }; &switch0 { ports { #address-cells = <1>; #size-cells = <0>; SWITCH_PORT(8, 1, internal) SWITCH_PORT(9, 2, internal) SWITCH_PORT(10, 3, internal) SWITCH_PORT(11, 4, internal) SWITCH_PORT(12, 5, internal) SWITCH_PORT(13, 6, internal) SWITCH_PORT(14, 7, internal) SWITCH_PORT(15, 8, internal) port@24 { reg = <24>; label = "lan9"; phy-handle = <&phy24>; phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sfp0>; }; port@26 { reg = <26>; label = "lan10"; phy-handle = <&phy26>; phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sfp1>; }; port@28 { ethernet = <ðernet0>; reg = <28>; phy-mode = "internal"; fixed-link { speed = <1000>; full-duplex; }; }; }; };