From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 13 Sep 2022 00:56:24 +0100 Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981 Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. Signed-off-by: Daniel Golle --- drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++- 1 file changed, 198 insertions(+), 4 deletions(-) --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -150,6 +150,21 @@ #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) +/* + * Layout of the fuses providing the calibration data + * These macros could be used for MT7981 and MT7986. + */ +#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) +#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff) +#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) +#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) +#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) +#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) +#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) +#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) +#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) +#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) + enum { VTS1, VTS2, @@ -163,6 +178,7 @@ enum { enum mtk_thermal_version { MTK_THERMAL_V1 = 1, MTK_THERMAL_V2, + MTK_THERMAL_V3, }; /* MT2701 thermal sensors */ @@ -245,6 +261,27 @@ enum mtk_thermal_version { /* The calibration coefficient of sensor */ #define MT8183_CALIBRATION 153 +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT7986_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT7986 */ +#define MT7986_NUM_SENSORS 1 + +/* The number of banks in the MT7986 */ +#define MT7986_NUM_ZONES 1 + +/* The number of sensing points per bank */ +#define MT7986_NUM_SENSORS_PER_ZONE 1 + +/* MT7986 thermal sensors */ +#define MT7986_TS1 0 + +/* The number of controller in the MT7986 */ +#define MT7986_NUM_CONTROLLER 1 + +/* The calibration coefficient of sensor */ +#define MT7986_CALIBRATION 165 + struct mtk_thermal; struct thermal_bank_cfg { @@ -279,6 +316,7 @@ struct mtk_thermal { struct clk *clk_peri_therm; struct clk *clk_auxadc; + struct clk *clk_adc_32k; /* lock: for getting and putting banks */ struct mutex lock; @@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; +/* MT7986 thermal sensor data */ +static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; +static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; +static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; +static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; +static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; +static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8 .version = MTK_THERMAL_V1, }; +/* + * MT7986 uses AUXADC Channel 11 for raw data access. + */ +static const struct mtk_thermal_data mt7986_thermal_data = { + .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, + .num_banks = MT7986_NUM_ZONES, + .num_sensors = MT7986_NUM_SENSORS, + .vts_index = mt7986_vts_index, + .cali_val = MT7986_CALIBRATION, + .num_controller = MT7986_NUM_CONTROLLER, + .controller_offset = mt7986_tc_offset, + .need_switch_bank = true, + .bank_data = { + { + .num_sensors = 1, + .sensors = mt7986_bank_data, + }, + }, + .msr = mt7986_msr, + .adcpnp = mt7986_adcpnp, + .sensor_mux_values = mt7986_mux_values, + .version = MTK_THERMAL_V3, +}; + /** * raw_to_mcelsius - convert a raw ADC value to mcelsius * @mt: The thermal controller @@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk return (format_2 - tmp) * 100; } +static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + if (raw == 0) + return 0; + + raw &= 0xfff; + tmp = 100000 * 15 / 16 * 10000; + tmp /= 4096 - 512 + mt->adc_ge; + tmp /= 1490; + tmp *= raw - mt->vts[sensno] - 2900; + + return mt->degc_cali * 500 - tmp; +} + /** * mtk_thermal_get_bank - get bank * @bank: The bank @@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature( if (mt->conf->version == MTK_THERMAL_V1) { temp = raw_to_mcelsius_v1( mt, conf->bank_data[bank->id].sensors[i], raw); - } else { + } else if (mt->conf->version == MTK_THERMAL_V2) { temp = raw_to_mcelsius_v2( mt, conf->bank_data[bank->id].sensors[i], raw); + } else { + temp = raw_to_mcelsius_v3( + mt, conf->bank_data[bank->id].sensors[i], raw); } /* @@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2( return 0; } +static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) +{ + if (!CALIB_BUF1_VALID_V3(buf[1])) + return -EINVAL; + + mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]); + mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); + mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); + mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); + mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); + mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); + mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); + mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); + + if (CALIB_BUF1_ID_V3(buf[1]) == 0) + mt->o_slope = 0; + + return 0; +} + static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) { @@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d /* Start with default values */ mt->adc_ge = 512; + mt->adc_oe = 512; for (i = 0; i < mt->conf->num_sensors; i++) mt->vts[i] = 260; mt->degc_cali = 40; @@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d if (mt->conf->version == MTK_THERMAL_V1) ret = mtk_thermal_extract_efuse_v1(mt, buf); - else + else if (mt->conf->version == MTK_THERMAL_V2) ret = mtk_thermal_extract_efuse_v2(mt, buf); + else + ret = mtk_thermal_extract_efuse_v3(mt, buf); if (ret) { dev_info(dev, "Device not calibrated, using default calibration values\n"); @@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the .data = (void *)&mt7622_thermal_data, }, { + .compatible = "mediatek,mt7986-thermal", + .data = (void *)&mt7986_thermal_data, + }, + { .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, }, { @@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat if (IS_ERR(mt->clk_auxadc)) return PTR_ERR(mt->clk_auxadc); + if (mt->conf->version == MTK_THERMAL_V3) { + mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k"); + if (IS_ERR(mt->clk_adc_32k)) + return PTR_ERR(mt->clk_adc_32k); + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(mt->thermal_base)) @@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat if (ret) return ret; + if (mt->conf->version == MTK_THERMAL_V3) { + ret = clk_prepare_enable(mt->clk_adc_32k); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret); + return ret; + } + } + ret = clk_prepare_enable(mt->clk_auxadc); if (ret) { dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); - return ret; + goto err_disable_clk_adc_32k; } ret = clk_prepare_enable(mt->clk_peri_therm); @@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat goto err_disable_clk_auxadc; } - if (mt->conf->version == MTK_THERMAL_V2) { + if (mt->conf->version == MTK_THERMAL_V2 || + mt->conf->version == MTK_THERMAL_V3) { mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); } @@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm: clk_disable_unprepare(mt->clk_peri_therm); err_disable_clk_auxadc: clk_disable_unprepare(mt->clk_auxadc); +err_disable_clk_adc_32k: + if (mt->conf->version == MTK_THERMAL_V3) + clk_disable_unprepare(mt->clk_adc_32k); return ret; } @@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla clk_disable_unprepare(mt->clk_peri_therm); clk_disable_unprepare(mt->clk_auxadc); + if (mt->conf->version == MTK_THERMAL_V3) + clk_disable_unprepare(mt->clk_adc_32k); + return 0; }