// SPDX-License-Identifier: GPL-2.0-only OR MIT /dts-v1/; #include #include #include #include "mt7986a.dtsi" / { compatible = "acelink,ew-7886cax", "mediatek,mt7986a"; model = "Acelink EW-7886CAX"; aliases { serial0 = &uart0; led-boot = &led_status_blue; led-running = &led_status_green; led-upgrade = &led_status_red; led-failsafe = &led_status_red; }; chosen { stdout-path = "serial0:115200n8"; }; memory@40000000 { reg = <0 0x40000000 0 0x20000000>; device_type = "memory"; }; keys { compatible = "gpio-keys"; key-restart { label = "Reset"; gpios = <&pio 7 GPIO_ACTIVE_LOW>; linux,code = ; }; }; leds { compatible = "gpio-leds"; led_status_red: led-0 { function = LED_FUNCTION_STATUS; color = ; gpios = <&pio 18 GPIO_ACTIVE_HIGH>; }; led_status_green: led-1 { function = LED_FUNCTION_STATUS; color = ; gpios = <&pio 19 GPIO_ACTIVE_HIGH>; }; led_status_blue: led-2 { function = LED_FUNCTION_STATUS; color = ; gpios = <&pio 20 GPIO_ACTIVE_HIGH>; }; }; }; &crypto { status = "okay"; }; ð { status = "okay"; mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "2500base-x"; phy-handle = <&phy6>; nvmem-cells = <&macaddr>; nvmem-cell-names = "mac-address"; }; mdio-bus { reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; reset-delay-us = <50000>; reset-post-delay-us = <20000>; #address-cells = <1>; #size-cells = <0>; /* Maxlinear GPY211C */ phy6: phy@6 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <6>; }; }; }; &pcie_phy { status = "okay"; }; &pio { spi_flash_pins: spi-flash-pins-33-to-38 { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; drive-strength = <8>; mediatek,pull-up-adv = <0>; /* bias-disable */ }; conf-pd { pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; drive-strength = <8>; mediatek,pull-down-adv = <0>; /* bias-disable */ }; }; wf_2g_5g_pins: wf_2g_5g-pins { mux { function = "wifi"; groups = "wf_2g", "wf_5g"; }; conf { pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA"; drive-strength = <4>; }; }; wf_dbdc_pins: wf-dbdc-pins { mux { function = "wifi"; groups = "wf_dbdc"; }; conf { pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA"; drive-strength = <4>; }; }; }; &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; flash@0 { compatible = "spi-nand"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <52000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { reg = <0x0 0x100000>; label = "bootloader"; read-only; }; partition@100000 { reg = <0x100000 0x80000>; label = "u-boot-env"; }; partition@180000 { compatible = "nvmem-cells"; reg = <0x180000 0x200000>; label = "factory"; read-only; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; eeprom: eeprom@0 { reg = <0x0 0x1000>; }; macaddr: macaddr@4 { reg = <0x4 0x6>; }; }; }; partition@380000 { reg = <0x380000 0x200000>; label = "fip"; }; partition@580000 { reg = <0x580000 0x4000000>; label = "ubi"; }; }; }; }; &trng { status = "okay"; }; &uart0 { status = "okay"; }; &watchdog { status = "okay"; }; &wifi { pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; nvmem-cells = <&eeprom>; nvmem-cell-names = "eeprom"; status = "okay"; };