#include "mt7620a.dtsi" #include #include / { compatible = "phicomm,psg1208", "ralink,mt7620a-soc"; model = "Phicomm PSG1208"; aliases { led-boot = &led_wps; led-failsafe = &led_wps; led-running = &led_wps; led-upgrade = &led_wps; }; leds { compatible = "gpio-leds"; led_wps: wps { label = "white:wps"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wlan { label = "white:wlan2g"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; }; }; keys { compatible = "gpio-keys"; reset { label = "reset"; gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; linux,code = ; }; }; }; &gpio1 { status = "okay"; }; &gpio3 { status = "okay"; }; &spi0 { status = "okay"; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; m25p,fast-read; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x0 0x30000>; read-only; }; partition@30000 { label = "u-boot-env"; reg = <0x30000 0x10000>; read-only; }; factory: partition@40000 { label = "factory"; reg = <0x40000 0x10000>; read-only; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; eeprom_factory_0: eeprom@0 { reg = <0x0 0x200>; }; eeprom_factory_8000: eeprom@8000 { reg = <0x8000 0x200>; }; macaddr_factory_4: macaddr@4 { reg = <0x4 0x6>; }; }; }; partition@50000 { compatible = "denx,uimage"; label = "firmware"; reg = <0x50000 0x7b0000>; }; }; }; }; &state_default { gpio { groups = "i2c", "spi refclk", "wled"; function = "gpio"; }; }; ðernet { pinctrl-names = "default"; pinctrl-0 = <&ephy_pins>; nvmem-cells = <&macaddr_factory_4>; nvmem-cell-names = "mac-address"; mediatek,portmap = "llllw"; }; &pcie { status = "okay"; }; &pcie0 { mt76@0,0 { reg = <0x0000 0 0 0 0>; nvmem-cells = <&eeprom_factory_8000>; nvmem-cell-names = "eeprom"; ieee80211-freq-limit = <5000000 6000000>; }; }; &wmac { nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; };